Z8018010VSG Datasheet, PDF (15/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
9
BUSACK—Bus Acknowledge (output, active Low). BUSACK indicates the requesting
device, the MPU address and data bus, and some control signals that enter their high-imped-
ance state.
BUSREQ—Bus Request (input, active Low). This input is used by
external devices (such as DMA controllers) to request access to the
system bus. This request demands a higher priority than NMI and is always recognized at the
end of the current machine cycle. This signal stops the CPU from executing further instruc-
tions and places address and data buses, and other control signals, into the high-impedance
state.
CKA0, CKA1—Asynchronous Clock 0 and 1 (bidirectional, active High). When in output
mode, these pins are the transmit and receive clock
outputs from the ASCI baud rate generators. When in input mode, these pins serve as the
external clock inputs for the ASCI baud rate generators. CKA0 is multiplexed with DREQ0,
and CKA1 is multiplexed with TEND0.
CKS—Serial Clock (bidirectional, active High). This line is the clock for the CSIO channel.
CLOCK—System Clock (output, active High). The output is used as a
reference clock for the MPU and the external system. The
frequency of this output is equal to one-half that of the crystal or input clock frequency.
CTS0–CTS1—Clear to send 0 and 1 (inputs, active Low). These lines are modem control
signals for the ASCI channels. CTS1 is
multiplexed with RXS.
D0–D7—Data Bus (bidirectional, active High, 3-state). D0–D7
constitute an 8-bit bidirectional data bus, used for the transfer of
information to and from I/O and memory devices. The data bus enters the high-impedance
state during reset and external bus acknowledge cycles.
DCD0—Data Carrier Detect 0 (input, active Low). A programmable modem control signal
for ASCI channel 0.
DREQ0, DREQ1. DMA Request 0 and 1 (input, active Low). DREQ is used to request a
DMA transfer from one of the on-chip DMA channels. The DMA channels monitor these
inputs to determine when an external device is ready for a READ or WRITE operation. These
inputs can be programmed to be either level or edge sensed. DREQ0 is multiplexed with
CKA0.
E—Enable Clock (output, active High). Synchronous machine cycle clock output during bus
transactions.
EXTAL—External Clock Crystal (input, active High). Crystal oscillator connections. An
external clock can be input to the Z80180 on this pin when a crystal is not used. This input is
Schmitt-triggered.
HALT—HALT/SLEEP (output, active Low). This output is asserted after the CPU executes
either the HALT or SLEEP instruction, and is waiting for either nonmaskable or maskable
PS014004-1106
Overview