Z8018010VSG Datasheet, PDF (50/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
44
of CNTLB0 in a real-time, positive-logic fashion (HIGH = 1, LOW = 0). If bit 5 in the System
Configuration Register is 0 to auto-enable CTS0, and the pin is negated (High), the TDRE bit
is inhibited (forced to 0). Bit 5 of CNTLB1 reads back as 0.
If the SS2–0 bits in this register are not 111, and the BRG mode bit in the ASEXT register is 0,
then writing to this bit sets the prescale (PS) control. Under these circumstances, a 0 indi-
cates a divide-by-10 prescale function, while a 1 indicates divide-by-30. The bit resets to 0.
PEO: Parity Even Odd (bit 4)—PEO selects oven or odd parity. PEO does not affect the
enabling/disabling of parity (MOD1 bit of CNTLA). If PEO is cleared to 0, even parity is
selected. If PEO is set to 1, odd parity is selected. PEO is cleared to 0 during RESET.
DR: Divide Ratio (bit 3)—If the X1 bit in the ASEXT register is 0, this bit specifies the
divider used to obtain baud rate from the data sampling clock. If DR is reset to 0, divide- by-
16 is used, while if DR is set to 1, divide-by-64 is used. DR is cleared to 0 during RESET.
SS2,1,0: Source/Speed Select 2,1,0 (bits 2–0)—If these bits are 111, as they are after
RESET, the CKA pin is used as a clock input, and is divided by 1, 16, or 64 depending on the
DR bit and the X1 bit in the ASEXT register.
If these bits are not 111 and the BRG mode bit is ASEXT is 0, these bits specify a power-of-
two divider for the PHI clock as indicated in Table 12.
Setting or leaving these bits as 111 makes sense for a channel only when its CKA pin is
selected for the CKA function. CKAO/CKS features the CKAO function when bit 4 of the
System Configuration Register is 0. DCD0/CKA1 features the CKA1 function when bit 0 of
the Interrupt Edge register is 1.
Table 12. Divide Ratio
SS2 SS1 SS0 Divide Ratio
0
0
0
÷1
0
0
1
÷2
0
1
0
÷4
0
1
1
÷8
1
0
0
÷16
1
0
1
÷32
1
1
0
÷64
1
1
1
External Clock
PS014004-1106
Architecture