Z8018010VSG Datasheet, PDF (40/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
34
DMA Control Signals
ø
DREQi
(at level sense)
DREQi
(at level sense)
TENDi
ST
CPU or DMA READ/WRITE Cycle (Only DMA WRITE Cycle for TENDi)
T₁
T₂
T_W
T₃
T₁
45 46*1
45 46*2
47
*3 ₁₇
*4 ₁₈
48
Notes:
1. t_DRQS and t_DHQH are specified for the rising edge of clock followed by T₃.
2. t_DRQS and t_DHQH are specified for the rising edge of clock.
3. DMA cycle starts.
4. CPU cycle starts.
Figure 19. DMA Control Signals
PS014004-1106
Architecture