Z8018010VSG Datasheet, PDF (68/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
62
DMA I/O Address Register Channel 1B
Mnemonic IAR1B (Address 2D)
DMA I/O Address Register Channel 1B
32 1 0
——— —
DMA I/O Channel B Address
Figure 64. DMA I/O Address Register Channel 1B
DMA Status Register (DSTAT)
DSTAT is used to enable and disable DMA transfer and DMA termination interrupts. DSTAT
also indicates DMA transfer status, in other words, completed or in progress.
Mnemonic DSTAT (Address 30)
DMA Status Register (DSTAT: I/O Address = 30h)
Bit 7
6
5
4
3
2
1
0
DE1 DE0 DWE1 DWE0 DIE1 DIE0
DME
R/W R/W W
W R/W R/W
R
Figure 65. DMA Status Register (DSTAT: I/O Address = 30h)
DE1: DMA Enable Channel 1 (bit 7)—When DE1 = 1 and DME = 1, channel 1 DMA is
enabled. When a DMA transfer terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC.
When DE1 = 0 and the DMA interrupt is enabled (DIE1 = 1), a DMA interrupt request is
made to the CPU.
To perform a software WRITE to DE1, DWE1 must be written with 0 during the same register
WRITE access. Writing DE1 to 0 disables channel 1 DMA, but DMA is restartable. Writing
DE1 to 1 enables channel 1 DMA and automatically sets DME (DMA Main Enable) to 1.
DE1 is cleared to 0 during RESET.
DE0: DMA Enable Channel 0 (bit 6)—When DE0 = 1 and DME = 1, channel 0 DMA is
enabled. When a DMA transfer terminates (BCR0 = 0), DE0 is reset to 0 by the DMAC.
PS014004-1106
Architecture