Z8018010VSG Datasheet, PDF (74/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
68
When a TRAP interrupt occurs, the Z80180 operates as follows:
1. The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1.
2. The current Program Counter (PC) value, reflecting the location of the undefined
opcode, is saved on the stack.
3. The Z80180 vectors to logical address 0.
Note: If logical address 0000h is mapped to physical address 00000h, the vector is the
same as for RESET. In this case, testing the TRAP bit in ITC reveals whether the
restart at physical address 00000h was caused by RESET or TRAP.
All TRAP interrupts occur after fetching an undefined second opcode byte following one of
the prefix opcodes CBh, DDh, EDh, or FDh, or after fetching an undefined third opcode byte
following one of the double-prefix opcodes DDCBh or FDCBh.
The state of the Undefined Fetch Object (UFO) bit in ITC allows TRAP software to correctly
adjust the stacked PC, depending on whether the second or third byte of the opcode gener-
ated the TRAP. If UFO = 0, the starting address of the invalid instruction is equal to the
stacked PC-1. If UFO = 1, the starting address of the invalid instruction is equal to the stacked
PC-2.
φ
A₀–A₁₈ (A₁₉)
D₀–D₇
M1
MREQ
RD
WR
Restart
from 0000h
2nd Opcode
Fetch Cycle
PC Stacking
Opcode
Fetch Cycle
T₁ T₂ T₃ T_TP T_i T_i T_i T_i T_i T₁ T₂ T₃ T₁ T₂ T₃ T₁ T₂ T₃
PC
Undefined
Opcode
SP-1
PC_H
SP-2
PC_L
0000h
Figure 70. TRAP Timing—2^nd Opcode Undefined
TRAP Timing—2^nd Op Code Undefined
PS014004-1106
Architecture