DS790 Datasheet, PDF (9/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
Table 4: Core Registers (Cont’d)
Base Address + Offset
(hex)
Register Name
Access Type
Default
Value
(hex)
Description
C_BASEADDR + 0x68
IP Interrupt Enable
Register (IPIER)
R/W
0x0
IP interrupt enable register.
SYSMON Hard Macro Register Grouping⁽⁵⁾
C_BASEADDR + 0x200
Temperature
Read⁽⁶⁾
The 10-bit MSB justified result of
N/A
on-chip temperature measurement is
stored in this register.
C_BASEADDR + 0x204
V_CCINT
Read⁽⁶⁾
The 10-bit MSB justified result of
N/a
on-chip V_CCINT supply monitor
measurement is stored in this register.
C_BASEADDR + 0x208
V_CCAUX
Read⁽⁶⁾
The 10-bit MSB justified result of
N/A
on-chip V_CCAUX Data supply monitor
measurement is stored in this register.
C_BASEADDR + 0x20C
V_P/V_N
R/W⁽⁷⁾
When read: The 10-bit MSB justified
result of A/D conversion on the
dedicated analog input channel (Vp/Vn)
is stored in this register.
0x0
When written: A write to this register will
reset the SYSMON hard macro. No
specific data is required. Applicable
only when the Virtex-6 device is
targeted.
C_BASEADDR + 0x210
C_BASEADDR + 0x214
C_BASEADDR + 0x218
to 
C_BASEADDR + 0x21C
V_REFP
V_REFN
Undefined
Read⁽⁶⁾
Read⁽⁶⁾
N/A
0x0
0x0
Undefined
The 10-bit MSB justified result of an
A/D conversion on the reference input
V_REFP is stored in this register
The 10-bit MSB justified result of an
A/D conversion on the reference input
V_REFN is stored in this register.
These locations are unused and
contain invalid data.Do not Read or
Write to these registers.
C_BASEADDR + 0x220
Supply Offset
Read⁽⁶⁾
N/A
The calibration coefficient for the supply
sensor offset is stored in this register.
C_BASEADDR + 0x224
ADC Offset
Read⁽⁶⁾
The calibration coefficient for the ADC
N/A
offset calibration is stored in this
register.
C_BASEADDR + 0x228
Gain Error
Read⁽⁶⁾
N/A
The calibration coefficient for the gain
error is stored in this register.
C_BASEADDR + 0x22C
to 
C_BASEADDR + 0x23C
Undefined
These locations are unused and
N/A
Undefined contain invalid data.Do not Read or
Write to these registers.
C_BASEADDR + 0x240
V_AUXP[0]/V_AUXN[0]
Read⁽⁶⁾
The 10-bit MSB justified result of an
0x0
A/D conversion on the auxiliary analog
input 0 is stored in this register.
C_BASEADDR + 0x244
V_AUXP[1]/V_AUXN[1]
Read⁽⁶⁾
The 10-bit MSB justified result of an
0x0
A/D conversion on the auxiliary analog
input 1 is stored in this register.
DS790 March 1, 2011
www.xilinx.com
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Product Specification