DS790 Datasheet, PDF (4/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
The SYSMON hard macro is present in every Virtex-6 FPGA. The block diagram for the System Monitor ADC hard
macro on a Virtex-6 FPGA is shown in Figure 2.
X-Ref Target - Figure 2
DS790_02
Figure 2: Block Diagram of the System Monitor ADC Hard Macro
The AXI Sysmon ADC core is built around the dedicated System Monitor hard macro of the Virtex-6 device family.
The hard macro uses the 10-bit, 200-KSPS ADC internally for conversion of various analog data. The AXI Sysmon
ADC core is used to measure die temperature and voltage. Additionally, the AXI Sysmon ADC core provides ana-
log to digital conversion of up to 17 external channels. From a user point of view, the core is defined as a AXI Sys-
mon ADC which can monitor on-chip voltage and temperature, external analog voltages, or both.
The SYSMON hard macro consists of a Register File Interface (RFI) which in turn consists of status and control reg-
isters. Status registers are read-only and contain the results of analog-to-digital conversion of the on-chip sensors
and external channels. The status registers also store the maximum and minimum temperature and
VCCAUX/VCCINT voltages. The control registers are used to configure the SYSMON hard macro operation. SYS-
MON hard macro functionality, such as ADC operating modes, channel sequencer, and alarm limits, is controlled
through these registers. The first three registers in the control register block, also known as configuration registers,
are used to configure the SYSMON hard macro operating modes. In addition to the RFI of the hard macro, the AXI
Sysmon ADC core consists of a set of local register and optional interrupt registers.
The SYSMON hard macro provides channel sequencing, averaging, and filtering functions. Many of the 16-bit reg-
isters are not defined in the SYSMON hard macro RFI. An undefined value is returned if accessing a location which
is undefined.
In the SYSMON hard macro, a channel sequencer allows the user to specify the channels monitored (the sequence
order is fixed). Users can specify an averaging filter to reduce noise. There are programmable alarm thresholds for
the on-chip sensors, and if an on chip temperature or voltage is enabled and is outside the specified limit, an alarm
is activated.
Structurally, the AXI Sysmon ADC core consists of the SYSMON hard macro, the AXI4 Interface Module, the
Optional Interrupt Source Controller Module, the Soft Reset Module, the SYSMON Reset Register, and additional
logic to interface to the core. The Soft Reset Module provides a way for resetting the entire IP without disturbing the
entire system. The SYSMON Reset Register is provided to reset the SYSMON hard macro only.
All read and write operations to the configuration and limit registers are synchronized to the DCLK. The SYSMON
hard macro has an internal clock divider which divides DCLK by any integer ranging from 2 to 255 to generate
DS790 March 1, 2011
www.xilinx.com
4
Product Specification