DS790 Datasheet, PDF (19/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
More about Locally Generated Interrupt Bits in IPIER and IPISR
The interrupt bits ranging from the bit-9 to bit-0 in IPISR, as well as IPIER, are direct output signals of the SYSMON
hard macro. Signals such as OT Deactive (bit-8) and ALM[0] Deactive (bit-9) are locally generated in the core. These
two interrupts will be generated on the falling edge of the Over Temperature and AML[0] signals. The falling edge
of these two signals may be used to controlling external functions such as the fan or the air-conditioning of the sys-
tem. See Reference Documents for details about the significance of these interrupts.
SYSMON Hard Macro Register (DRP Register) Grouping
The SYSMON hard macro register set consists of all the registers present in the SYSMON hard macro on the Virtex-6
FPGAs. The addresses of these registers are mentioned in Table 4. Because these registers are 16-bit wide but the
processor data bus is 32-bit wide, the hard macro register data resides on the lower 16 bits of the 32-bit data bus as
shown in Figure 11. The 10-bit MSB aligned A/D converted value of different channels from the SYSMON hard
macro are left shifted and reside from bit position 15 to 6 of the processor data bus. The remaining bit positions from
5 to 0 should be ignored while considering the ADC data for different channels. Along with 16-bit data, JTAGMOD-
IFIED and JTAGLOCKED bits are passed which can be used by the software driver application to determine the
validity of the DRP read data. The JTAGMODIFIED bit is cleared when a DRP read/write operation through the
fabric is successful. A DRP read/write through the fabric fails if JTAGLOCKED = ’1’. The JTAGLOCKED signal is
independently controlled through JTAG TAP. It is expected that these SYSMON hard macro registers should be
accessed in their preferred access-mode only. The AXI Sysmon ADC core will not be able to differentiate any
non-preferred access to the SYSMON hard macro registers. For more information on these registers, see Reference
Documents section.
X-Ref Target - Figure 11
Undefined
JTAG
MODIFIED
16-bit Hard
Macro Data
(DRP Data - Do)
31
18 17 16 15
0
JTAG
LOCKED
Figure 11: SYSMON Hard Macro Register
DS790_11
DRP registers are accessed as part of cores local registers — these registers must be accessed through the core local
registers. Any attempt to access these registers in byte or half-word manner will return the error response from the
core.
Design Implementation
Target Technology
The intended target technology is the Virtex-6 family FPGAs.
Device Utilization and Performance Benchmarks
Core Performance
Because the AXI Sysmon ADC core will be used with other design modules in the FPGA, the utilization and timing
numbers reported in this section are estimates only. When the AXI Sysmon ADC core is combined with other
DS790 March 1, 2011
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Product Specification