DS790 Datasheet, PDF (20/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
designs in the system, the utilization of FPGA resources and timing of the AXI Sysmon ADC core design will vary
from the results reported here.
The AXI Sysmon ADC core resource utilization for various parameter combinations measured with the Virtex-6
FPGA as the target device are detailed in Table 13.
Table 13: Performance and Resource Utilization Benchmarks on the Virtex-6 FPGA (xc6vlx130t-ff1156-1)
Parameter Values (Other parameters at default values)
Device Resources
Performance
C_INCLUDE_INTR
0
Slice Flip-Flops
113
LUTs
107
F_Max (MHz)
200
1
181
183
200
Note:
1. For above utilization calculation, the C_DCLK_RATIO = 3 is used, while the AXI clock was targeted at 200 MHz.
X-Ref Target - Figure 12
Virtex-6 LX FPGA
MicroBlaze
Domain
(IC)
(DC)
MicroBlaze
Controller
Memory
Mappped
Interconnect
(AXI4)
AXI4 Full Domain
AXI DDR
Memory
Controller
AXI BRAM
Memory
D_LMB
I_LMB
BRAM
Controller
(DP)
Control
Interface
Subset
Interconnect
(AXI4-Lite)
AXI CDMA
AXI INTC
AXI GPIO
AXI UARTLite
Device Under
Test (DUT)
LEDs
RS232
MDM
AXI4-Lite Domain
DS790_13
Figure 12: Virtex-6 LX FPGA System with the AXI Sysmon ADC Core as the DUT
DS790 March 1, 2011
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Product Specification