DS790 Datasheet, PDF (3/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
The AXI Sysmon ADC core consists of following major blocks.
• AXI-Lite Interface Module
• SYSMON ADC Core Logic
• SYSMON Hard Macro
AXI-Lite Interface Module
The AXI-Lite Interface Module provides the AXI4-Lite decode service. Read and write transactions to and from the
AXI4 are translated into equivalent SYSMON ADC core logic and SYSMON hard macro transactions. The register
interfaces of the SYSMON ADC core logic connect to the AXI4 Interface Module.
Core Logic
The SYSMON ADC core logic provides necessary address decoding logic, control signal generation, and an inter-
face between the AXI4-Lite and SYSMON hard macro. The read and write requests, along with the address and data
(in case of a write transaction) from the AXI4 Interface Module, are transferred to either the Dynamic Reconfigura-
tion Port (DRP) registers of SYSMON hard macro or local registers in the IP along with the necessary control sig-
nals, such as DEN and DWE.
The SYSMON ADC core logic supports the inclusion and exclusion of the Interrupt Controller based on the generic
C_INCLUDE_INTR. The Interrupt Controller is included in the design if C_INCLUDE_INTR = 1.
There is new DRC limitation which has been imposed on the DCLK input clock of SYSMON hard macro on 
Virtex-6 devices. The DCLK for the hard macro must not exceed 80 MHz. To take care of this limitation, a new
parameter C_DCLK_RATIO is added in the design .
Based on the core frequency (when used in the system), this parameter must be set to make the DCLK less than or
equal to 80 MHz. These constraints are applicable only for Virtex-6 devices. The maximum clock at this port must
be 80 MHz. If this clock increases beyond 80 MHz, a DRC violation related to the SYSMON hard macro will be
raised, and the hard macro may not work properly.
The C_DCLK_RATIO supports range of values between 1 to 8. Internally, this value will be used to divide the AXI
Clock. It is strongly recommended that, the value of C_DCLK_RATIO should be set in such a way that, the DCLK
input frequency will be always equal to 80Mhz or close to 80Mhz. See Assigning the C_DCLK_RATIO Parameter,
page 21 before assigning the value to this parameter.
The SYSMON hard macro can be accessed via both the JTAG TAP (Test Access Port) and the AXI Sysmon ADC core.
When simultaneous access of the SYSMON hard macro occurs, the JTAGLOCKED port can be asserted High by
JTAG TAP, in which case the AXI Sysmon ADC core will not be allowed to do any read or write access from or to the
DRP. When the JTAGLOCKED port is again de-asserted through JTAG TAP, the AXI Sysmon ADC core is allowed
to perform read and write operation from or to the DRP.
This functionality is specially useful in applications where the user is configuring the DRP through JTAG TAP and
does not want the fabric (AXI Sysmon ADC core) to alter the configuration. The user can make JTAGLOCKED = ’1’
through JTAG TAP which blocks any read or write transactions from or to the DRP through fabric, thus ensuring a
non-destructive access through the JTAG TAP.SYSMON Hard Macro
DS790 March 1, 2011
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Product Specification