DS790 Datasheet, PDF (6/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
Table 1: Design Parameters (Cont’d)
Generic
Feature/Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
Notes:
1. The range C_BASEADDR to C_HIGHADDR is the address range for the AXI Sysmon ADC.This range is subject to restrictions to
accommodate the simple address decoding scheme that is employed: The size, C_HIGHADDR - C_BASEADDR + 1, must be a
power of two (2) and must be at least 0x400 to accommodate all AXI Sysmon ADC registers. However, a larger power than two (2)
may be chosen to reduce decoding logic. C_BASEADDR must be aligned to a multiple of the range size.
2. An invalid default is used to ensure that an actual value appropriate to the system is set.
3. Based on the core frequency, this parameter should be set to generate the DCLK frequency less than or equal to 80 MHz. For
more details, see Core Logic, page 3 and Assigning the C_DCLK_RATIO Parameter, page 21 before using this parameter.
I/O Signals
The AXI Sysmon ADC I/O signals are listed and described in Table 2.
Table 2: I/O Signal Descriptions
Port
Signal Name
Interface I/O
Initial
State
Description
AXI Global System Signals
P1 S_AXI_ACLK
AXI
I
-
AXI Clock
P2 S_AXI_ARESETN
AXI
I
-
AXI Reset, active LOW
AXI Write Address Channel Signals
P3
S_AXI_AWADDR[(C_S_AXI_
ADDR_WIDTH - 1) : 0]
AXI
I
-
AXI Write address: The write address bus gives the
address of the write transaction.
P4 S_AXI_AWVALID
Write address valid: This signal indicates that a
AXI
I
-
valid write address and control information are
available.
P5 S_AXI_AWREADY
Write address ready: This signal indicates that the
AXI
O
0 slave is ready to accept an address and associated
control signals.
AXI Write Channel Signals
S_AXI_WDATA[(C_S_AXI_
P6 _{DATA_WIDTH - 1) : 0]}
AXI
I
-
Write data
P7 ^{S_AXI_WSTB[((C_S_AXI_}
DATA_WIDTH/8) - 1) : 0]
AXI
I
-
Write strobes: This signal indicates which byte
lanes to update in memory.
P8 S_AXI_WVALID
AXI
I
-
Write valid: This signal indicates that valid write
data and strobes are available.
P9 S_AXI_WREADY
AXI
O
0
Write ready: This signal indicates that the slave
can accept the write data.
AXI Write Response Channel Signals
P10 S_AXI_BRESP[1 : 0]
Write response: This signal indicates the status of
the write transaction.
AXI
O
0 ^{“00“ - OKAY (normal response)}
“10“ - SLVERR (error response)
“11“ - DECERR (not issued by core)
P11 S_AXI_BVALID
AXI
O
0
Write response valid: This signal indicates that a
valid write response is available.
DS790 March 1, 2011
www.xilinx.com
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Product Specification