DS790 Datasheet, PDF (21/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 14.
Table 14: System Performance
Target FPGA
V6LX130t-1
Target F_MAX (MHz)
180
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Assigning the C_DCLK_RATIO Parameter
The parameter C_DCLK_RATIO has a range from 1 to 8. Any value in this range divides the AXI clock with the
value. The divided clock output of the BUFR primitive will be provided to the DCLK input of SYSMON hard
macro.
The maximum frequency limitation of 80 MHz is applicable only for Virtex-6 devices. See the SYSMON user guide
for Virtex-6 devices for maximum operating DCLK clock frequencies.
Along with the DCLK clock, Configuration Register 2 can be set for internal clock division of DCLK. The DCLK
clock input is further divided by this configuration register which is used as the clock for internal operation of the
SYSMON macro.
The internal operation speed of the SYSMON macro will now be decided by the Configuration Register 2 settings.
When a Virtex-6 device is targeted, the DCLK clock input to the macro can be a maximum of 80 MHz. It is recom-
mended to have the core frequency and DCLK clock be an even integer ratio (for example, core frequency = 200
MHz, C_CLK_RATIO = 4 making the DCLK = 50 MHz). If these are not an even integer ratio, then the macro will
generate a DRC error. The Configuration Register 2 of the SYSMON hard macro decides the internal operating fre-
quency of the macro.
Setting DCLK and Configuration Register 2 decides the internal clock of the SYSMON macro. It is recommended to
read the SYSMON user guide before setting any of the above mentioned values.
User Application Examples
This section provides examples on configuring AXI Sysmon ADC core in either continuous cycling of sequence or
single channel (continuous or event driven) mode. It is assumed that the user is aware with the AXI Sysmon ADC
core register descriptions given in Table 4 on page 8.
Continuous Cycling Of Sequence Mode Example
To configure the AXI Sysmon ADC core in Continuous Cycling of Sequence Mode, set the SEQ1 and SEQ0 bits in
Configuration Register 1 to ’1’ and ’0’ respectively. The specific value written to registers may vary depending upon
the need of application. Below is the configuration example for monitoring the On-Chip Temperature, V_CCINT =,
and V_CCAUX channel in the continuous cycling of sequence mode with the clock ratio set to 32.
1. Issue a software reset by writing the data word 0x0000_000A to the SRR. This asserts the reset of AXI Sysmon
ADC core for 16 AXI clock cycles.
2. Write 0x0000_0000 to Configuration Register 0. This configures the SYSMON hard macro in continuous
sampling mode.
DS790 March 1, 2011
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Product Specification