DS790 Datasheet, PDF (23/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
Single Channel Mode Examples
To configure the AXI Sysmon ADC core in single channel mode, set both SEQ1 and SEQ0 bits in configuration reg-
ister 1 to ’1’. The single channel operation can be programmed to operate either in the event-driven sampling mode
or continuous sampling mode by setting the EC bit in the configuration register to 0 to ’1’ or ’0’.
Should this be register 0 instead of register to 0?
Single Channel Event-Driven Sampling Mode Example
To configure the AXI Sysmon ADC core in the single channel event-driven sampling mode, set the EC bit in the con-
figuration register 0 to ’1’.
The specific value written to the registers may vary depending upon the need of the application. In addition, if the
On-Chip temperature or voltages are monitored, configure the alarm registers with the appropriate values before
writing to the configuration registers. The subsequent numbered instructions outline the configuration example for
monitoring the V_P/V_N channel with the clock ratio set to 32.
1. Issue a software reset by writing the data word 0x0000_000A to the SRR. This asserts the reset of the AXI
Sysmon ADC core for 16 clock cycles.
2. If an interrupt controller is present, such as C_INCLUDE_INTR = 1, write 0x8000_0000 to the GIER to enable
globally the interrupts.
3. Writing 0x0000_00FF to the IPIER to enable the operational interrupts.
4. Write 0x0000_0203 to configuration register 0. This configures the SYSMON hard macro with no averaging,
unipolar mode, event driven sampling, and selects channel 3 (V_P/V_N), for conversion.
5. Write 0x0000_3000 to Configuration Register 1. This configures the SYSMON hard macro in single channel
mode resulting in calibration disabled and alarm outputs enabled.
6. Write 0x0000_2000 to Configuration Register 2. This configures the SYSMON hard macro to have ADCCLK =
DCLK/32.
7. Read Status Register (SR) to reset EOC/EOS signal set by any previous conversions.
8. If interrupt controller is present, read IPISR to learn the value set by any previous conversions. For this
application, assume that the value read is 0x0000_003E.
9. Write 0x0000_003E to IPISR to toggle the bits which are ’1’, so that the new value of IPISR becomes 0x0000_0000.
10. Conversion Start can be signalled by writing 0x0000_0001 to the CONVSTR or by making the external CONVST
port = ’1’.
11. Reset the CONVSTR by writing 0x0000_0000 to it or by making CONVST port = ’0’ depending upon which type
of trigger (either CONVSTR register or CONVST port) is used for conversion start.
12. Read SR. If conversion is completed, the EOC bit in SR will be set to ’1’. If the interrupt controller is present, the
EOC bit in the IPISR is also set to ’1’.
13. Read the converted value of channel 3 (V_P/V_N) from address C_BASEADDR + 0x20C.
Single Channel Continuous Sampling Mode Example
To configure AXI Sysmon ADC core in Single Channel Continuous Sampling Mode, EC bit in Configuration Regis-
ter 0 should be set to ’0’. The specific value written to registers may vary depending upon the need of application.
Also if On-Chip temperature or voltages are monitored then Alarm registers should be configured with appropriate
values before writing to Configuration Registers. Below is the configuration example for monitoring V_P/V_N chan-
nel with clock ratio set to 32.
1. Issue a software reset by writing the data word 0x0000_000A to the SRR. This asserts the reset of AXI Sysmon
ADC core for 16 clock cycles.
DS790 March 1, 2011
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Product Specification