DS790 Datasheet, PDF (12/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
Table 4: Core Registers (Cont’d)
Base Address + Offset
(hex)
Register Name
C_BASEADDR + 0x344
Alarm Threshold
Register 1
C_BASEADDR + 0x348
Alarm Threshold
Register 2
C_BASEADDR + 0x34C
Alarm Threshold
Register 3
C_BASEADDR + 0x350
Alarm Threshold
Register 4
C_BASEADDR + 0x354
Alarm Threshold
Register 5
C_BASEADDR + 0x358
C_BASEADDR + 0x35C
C_BASEADDR + 0x360
to 
C_BASEADDR + 0x3FC
Alarm Threshold
Register 6
Alarm Threshold
Register 7
Undefined
Access Type
R/W
R/W
R/W^(9)(10)
R/W
R/W
R/W
R/W
Default
Value
(hex)
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
The 10-bit MSB justified alarm
threshold register 1 
(V_CCINT Upper).
The 10-bit MSB justified alarm
threshold register 2
(V_CCAUX Upper).
The 12-bit MSB justified alarm
threshold register 3
(OT Upper).
The 10-bit MSB justified alarm
threshold register 4 
(Temperature Lower).
The 10-bit MSB justified alarm
threshold register 5 
(V_CCINT Lower).
The 10-bit MSB justified alarm
threshold register 6
(V_CCAUX Lower).
The 10-bit MSB justified alarm
threshold register 7 (OT Lower).
N/A
Undefined Do not Read or Write to these registers.
Notes:
1. Reading of this register returns undefined value.
2. Writing into this register has no effect.
3. Used in event-driven sampling mode only.
4. TOW = Toggle On Write. Writing a ’1’ to a bit position within the register causes the corresponding bit position in the register to
toggle.
5. These are 16-bit registers internal to SYMON hard macro. These are mapped to lower half word boundary on 32-bit AXI Sysmon
ADC core registers. For more details refer System Monitor Register File Interface section in Reference Documents.
6. Writing to this SYSMON hard macro register is not allowed. The SYSMON ADC hard macro data registers are 16-bits in width. The
SYSMON hard macro specification guarantees the first 10-MSB bits accuracy, therefore only these bits are used for reference.
7. Writing to this register will reset the SYSMON hard macro. No specific data pattern is required to reset the SYSMON hard macro.
Reading of this register will give the details of Vp/Vn port.
8. See Reference Documents for setting the different bits available in configuration registers for Virtex-6 devices.
9. The OT Upper register is available only in Virtex-6 FPGA devices. This register location is N/A when Virtex-5 devices are targeted.
10. The OT Upper register is a user configurable register for upper threshold level of temperature. If this register is left un-configured,
then the SYSMON will consider 125⁰C as the upper threshold value for OT. Note that while configuring this register, the last 4-bits
must be set to 0011, for example, Alarm Threshold Register 3[3:0] = 0011. In addition, the upper 12 bits of this register are user
configurable.
11. The timeout counter is not included in the core logic. Targeting the register space where there is no register may cause no response
from the core, and the system may wait indefinitely. This is an important factor in creating designs.
Local Register Grouping
It is expected that the AXI Sysmon ADC core registers will be accessed in their preferred-access mode only. If the
write attempt is made to read-only registers, there will not be any effect on the register contents. If the write-only
registers are read, it will result in undefined data. All the internal registers of the core must be accessed in 32-bit for-
mat. If any other kind of access, such as half word or byte access, is done for the local 32-bit registers of the AXI Sys-
mon ADC core, the transaction will be completed with the generation of error for the corresponding transaction.
DS790 March 1, 2011
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Product Specification