DS790 Datasheet, PDF (13/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
Software Reset Register (SRR)
The Software Reset Register permits the programmer to reset the AXI Sysmon ADC core including the SYSMON
hard macro output ports (except JTAG related outputs), independently of other IP cores in the systems. To activate
the software reset, the value 0x0000_000A must be written to the register. Any other access, read or write, has unde-
fined results. The bit assignment in the software reset register is shown in Figure 3 and described in Table 5.
X-Ref Target - Figure 3
31
0
Reset
Figure 3: Software Reset Register
DS790_03
Table 5: Software Reset Register Description (C_BASEADDR + 0x00)
Bit(s) Name
Core
Access
Reset
Value
Description
0-31
Reset
Write only
N/A
The only allowed operation on this register is a write of 0x0000_000A, which
resets the AXI Sysmon ADC core. The reset is active only for 16 clock cycles.
Status Register (SR)
The Status Register (SR) contains the AXI Sysmon ADC core channel status, EOC, EOS, and JTAG access signals.
This register is read only. Any attempt to write the bits of the register will not change the bits. The Status Register
bit definitions are shown in Figure 4 and explained in Table 6.
X-Ref Target - Figure 4
Undefined
JTAG
LOCKED
JTAGBUSY
EOS
CH4
CH2
CH0
31
11 10 9 8 7 6 5 4 3 2 1 0
JTAG BUSY EOC CH3 CH1
MODIFIED
DS790_04
Figure 4: Status Register
Table 6: Status Register (C_BASEADDR + 0x04)
Bit(s)
Name
Core
Access
Reset
Value
Description
31 - 11 Undefined
N/A
N/A Undefined.
10
JTAGBUSY
Read
’0’
Used to indicate that a JTAG DRP transaction is in progress.
9 JTAG MODIFIED Read
Used to indicate that a write to DRP through JTAG interface has
’0’
occurred. This bit is cleared when a successful DRP read/write
operation through fabric is performed. The DRP read/write through
fabric fails, if JTAGLOCKED = ’1’.
8
JTAG LOCKED
Read
’0’
Used to indicate that a DRP port lock request has been made by the
Joint Test Action Group (JTAG) interface.
7
BUSY
Read
N/A
ADC busy signal: This signal transitions high during an ADC
conversion.
DS790 March 1, 2011
www.xilinx.com
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Product Specification