DS790 Datasheet, PDF (15/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
CONVST Register (CONVSTR)
The CONVST Register (CONVSTR) is used for initiating a new conversion in the event-driven sampling mode. The
output of this register is logically OR’ed with external the CONVST input signal. The attempt to read this register
will result un-defined data. The CONVST Register bit definitions are shown in Figure 6 and explained in Table 8.
X-Ref Target - Figure 6
Undefined
CONVST
31
10
DS790_06
Figure 6: CONVST Register
Table 8: CONVST Register (C_BASEADDR + 0x0C)
Bit(s) Name
Core
Access
Reset
Value
Description
31 - 1 Undefined
N/A
N/A Undefined.
0 CONVST
Write
A rising edge on the CONVST input initiates the start of the ADC conversion
’0’
in the event-driven sampling mode. For a selected channel, the CONVST bit
in the register must be set to ’1’ and again reset to ’0’ to start a new conversion
cycle. The conversion cycle ends with EOC bit going High.
SYSMON Reset Register (SYSMONRR)
The SYSMON Reset Register (SYSMONRR) is used to reset the SYSMON hard macro only. As soon as the reset is
released, the ADC begins with a new conversion. If sequencing is enabled, this conversion is the first in the
sequence. This register resets the OT and ALM[n] output from the SYSMON hard macro. This register does not reset
the interrupt registers if they are included in the design. Also note that any reset from the fabric does not affect the
RFI (Register File Interface) contents of the SYSMON hard macro. The attempt to read this register will result in
un-defined data. The SYSMON Reset Register bit definitions are shown in Figure 7 and explained in Table 9.
X-Ref Target - Figure 7
Undefined
SYSMON
Reset
31
10
Figure 7: SYSMON Reset Register
DS790_07
Table 9: SYSMON Reset Register (C_BASEADDR + 0x10)
Bit(s)
Name
Core
Access
Reset
Value
Description
31 - 1
Undefined
N/A
N/A Undefined.
0 SYSMON Reset
Write
’0’
Writing ’1’ to this bit position resets the SYSMON hard macro. The
reset is released only after ’0’ is written to this register.
Interrupt Controller Register Grouping
When C_INCLUDE_INTR = ’1’, the Interrupt Controller Module is included in the AXI Sysmon ADC core design.
The AXI Sysmon ADC has a number of distinct interrupts that are sent to the Interrupt Controller Module which is
one of the sub-modules of the AXI Sysmon ADC core. The Interrupt Controller Module allows each interrupt to be
DS790 March 1, 2011
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Product Specification