DS790 Datasheet, PDF (2/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
Functional Description
The top-level block diagram for the AXI Sysmon ADC core is shown in Figure 1.
X-Ref Target - Figure 1
AXI4-Lite
SYSMON ADC Core Logic
DCLK_ext_clk
CONVST
Register
OR
Logic
SYSMON
Hard Macro
DCLK
CONVST
AXI-Lite
Interface
32
IP2INTC_lrpt
SPLB_Rst
SysMon Reset
Register
Software Reset
Register
Reset
Logic
Status
Register
5
Data
Register
Alarm
Register
16
3
16
7
DEN and DWE
Control Register
Interrupt Controller
Interrupt Regiser
3
(GIER)
Interrupt Regiser
(IPISR)
Interrupt Regiser
(IPIER)
RESET
JTAGBUSY
JTAGLOCKED
JTAGMODIFIED
BUSY
EOC
EOS
CHANNEL[4:0]
D0[15:0]
ALM[2:0]
OT
D1[15:0]
DADDR[6:0]
DEN
DWE
DRDY
CONVSTCLK
ALM[2:0]
OT
EOS
EOC
JTAGLOCKED
JTAGMODIFIED
Figure 1: Block Diagram of the AXI Sysmon ADC Core
15
VAUXN
[15:0]
15
VAUXP
[15:0]
ALARM
[2:0]
DS790_01
DS790 March 1, 2011
www.xilinx.com
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Product Specification