DS790 Datasheet, PDF (22/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
3. Write 0x0000_2000 to Configuration Register 1. This configures the SYSMON hard macro in continuous cycling
of sequence mode which results in all calibration disabled and all alarm outputs enabled.
4. Write 0x0000_2000 to Configuration Register 2. This configures the SYSMON hard macro to have ADCCLK =
DCLK/32.
5. Read the Status Register (SR) to reset EOC/EOS signal set by any previous conversions.
6. If an interrupt controller is present, read the IPISR to learn the value set by any previous conversions. Assume
that for this application, the value read is 0x0000_003E.
7. Write 0x0000_003E to IPISR to toggle the bits which are ’1’ so that the new value of IPISR becomes 0x0000_0000.
8. If an interrupt controller is present, for example, C_INCLUDE_INTR = 1, perform a global enabling of
interrupts by writing 0x8000_0000 to the GIER.
9. Write 0x0000_00FF to the IPIER to enable the operational interrupts.
10. Write 0x0000_0700 to Sequence Register 0 and 0x0000_0000 to Sequence Register 1. This configures SYSMON
hard macro for monitoring On-Chip Temperature, V_CCINT and V_CCAUX channel.
11. Write 0x0000_0000 to Sequence Register 2 and 3. This disables ADC channel averaging.
12. Write 0x0000_0000 to Sequence Register 4 and 5. This configures the ADC channel in unipolar input mode.
13. Write 0x0000_0000 to Sequence Register 6 and 7. This configures the ADC channel acquisition time to four
ADCCLK cycles.
14. Write 0x0000_A900 to Alarm Register 0. This configures the upper limit for the temperature alarm, which for
this application is set to 60^o C.
15. Write 0x0000_9980 to Alarm Register 1. This configures the upper limit for the V_CCINT alarm, which for this
application is set to 1.8 V.
16. Write 0x0000_EE80 to Alarm Register 2. This configures the upper limit for the V_CCAUX alarm, which for this
application is set to 2.8 V.
17. Write 0x0000_A000 to Alarm Register 4. This configures the lower limit for the temperature alarm, which for
this application is set to 42^o C.
18. Write 0x0000_4400 to Alarm Register 5. This configures the lower limit for the V_CCINT alarm, which for this
application is set to 0.8 V.
19. Write 0x0000_9980 to Alarm Register 6. This configures the lower limit for the V_CCAUX alarm, which for this
application is set to 1.8 V.
20. Write 0x0000_A180 to Alarm Register 7. This configures the lower limit for the OT alarm, which for this
application is set to 45^o C.
21. The Alarm Register 3 will be active only in case of the Virtex-6 device. When the Virtex-6 FPGA is targeted, this
register is used to set the upper limit of OT. The OT upper is a 12 bit register. Set the lower 4 bits to “0011”. If this
register is left un-initialized, 125^o C will be considered as the default upper temperature for OT.
22. Write 0x0000_2000 to Configuration Register 1. This configures the SYSMON hard macro in continuous cycling
of sequence mode, all calibration disabled, and all alarm outputs enabled. Perform a write operation on this
register to enable the sequence written to sequence registers. [Refer System Monitor User Guide for bits of
Configuration Register 0, when targeted for Virtex-6 devices]
23. Read SR. If the present conversion cycle is completed, EOS bit in SR is set to ’1’. If the interrupt controller is
present, the EOS bit in IPISR is also set to ’1’.
24. Read converted value of the On-Chip Temperature, V_CCINT and V_CCAUX channel, from address C_BASEADDR
+ 0x200, C_BASEADDR + 0x204, and C_BASEADDR + 0x208, respectively.
DS790 March 1, 2011
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Product Specification