DS790 Datasheet, PDF (5/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
ADCCLK. ADCCLK is an internal clock used by the ADC. Because an internal clock divider is provided, the DCLK
frequency can be in the range of 2 MHz to 80 MHz. See the Virtex-6 FPGA data sheets for the maximum operating
frequency of the SYSMON ADC core.
The SYSMON hard macro operates in either an event driven or continuous sampling mode. In event the driven
sampling mode, the conversion process is initiated on the rising edge of CONVST. The AXI Sysmon ADC core sup-
ports this operation by providing a rising edge signal on the external CONVST port or by writing into the CONVST
register. In the continuous sampling mode, the ADC continuous to carry out a conversion on the selected analog
inputs as long as the ADCCLK (DCLK) is present. For more information on the SYSMON hard macro, see [Ref 1].
Design Parameters
To allow the user to obtain a AXI Sysmon ADC core that is uniquely tailored for their system, certain features can
be parameterized in the AXI Sysmon ADC design. This allows the user to configure a design that utilizes the
resources required by the system only and that operates with the best possible performance. The features that can
be parameterized are as shown in Table 1.
Inferred Parameters
In addition to the parameters listed in Table 1, there are also parameters that are inferred for each AXI interface in
the EDK tools. Through the design, these EDK-inferred parameters control the behavior of the AXI Interconnect.
For a complete list of the interconnect settings related to the AXI interface, see the DS768, AXI Interconnect IP Data
Sheet.
Table 1: Design Parameters
Generic
Feature/Description
G1 Target FPGA family
G2 AXI Base Address
G3 AXI High Address
G4 AXI Address Bus Width
G5 AXI Data Bus Width
G6
Include/Exclude 
interrupt support
G7
File name for Analog input
stimuli
G8 DCLK clock division ratio
Parameter Name
Allowable Values
System Parameters
C_FAMILY
virtex6
AXI4 Parameters
C_BASEADDR
Valid Address⁽¹⁾
C_HIGHADDR
Valid Address⁽¹⁾
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
AXI Sysmon ADC Parameters
C_INCLUDE_INTR
0 = Exclude interrupt
support
1 = Include interrupt
support
C_SIM_MONITOR_FILE string
C_DCLK_RATIO
1,2,3,4,5,6,7,8⁽³⁾
Default
Value
VHDL
Type
virtex6
string
None⁽²⁾
None⁽²⁾
32
32
std_logic_
vector
std_logic_
vector
integer
integer
1
integer
Design.txt
2⁽³⁾
string
string
DS790 March 1, 2011
www.xilinx.com
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Product Specification