DS790 Datasheet, PDF (17/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
Table 11: IP Interrupt Status Register (IPISR) Description (C_BASEADDR + 0x60)
Bit(s)
Name
Access
Reset
Value
Description
31 - 10
Undefined
N/A
N/A Undefined.
9
ALM[0] Deactive R/TOW⁽¹⁾
ALM[0] Deactive Interrupt: This signal indicates that the falling edge
of the ALM[0] (ALM[0] indicates that the user temperature range
violation) signal is detected. It is cleared by writing ’1’ to this bit
’0’ position.
The ALM[0] Deactive signal is generated locally from the core. This
signal indicates that the SYSMON macro has deactivated the user
temperature violation signal output.
OT Deactive Interrupt: This signal indicates that the falling edge of
the Over Temperature signal is detected. It is cleared by writing ’1’ to
8
OT Deactive
R/TOW⁽¹⁾
’0’
this bit position.
The OT Deactive signal is generated locally from the core. This signal
indicates that the SYSMON macro has deactivated the Over
Temperature signal output.
7
JTAG MODIFIED R/TOW⁽¹⁾⁽²⁾
JTAGMODIFIED Interrupt: This signal indicates that a write to DRP
’0’ through JTAG interface has occurred. It is cleared by writing ’1’ to this
bit position.
JTAGLOCKED Interrupt: This signal is used to indicate that a DRP
6
JTAG LOCKED R/TOW⁽¹⁾⁽²⁾
’0’ port lock request has been made by the Joint Test Action Group
(JTAG) interface.
End of Conversion signal Interrupt: This signal transitions to an active
5
EOC
R/TOW⁽¹⁾⁽²⁾
N/A High at the end of an ADC conversion when the measurement is
written to the SYSMON hard macro’s status register.
End of Sequence Interrupt: This signal transitions to an active High
4
EOS
R/TOW⁽²⁾
N/A when the measurement data from the last channel in the auto
sequence is written to the status registers.
System Monitor VCCAUX-sensor Interrupt: The System Monitor
3
ALM[2]
R/TOW⁽²⁾
’0’ VCCAUX-sensor alarm output interrupt occurs when the VCCAUX
exceeds the user defined threshold.
System Monitor VCCINT-sensor Interrupt: The System Monitor
2
ALM[1]
R/TOW⁽²⁾
’0’ VCCINT-sensor alarm output interrupt occurs when the VCCINT
exceeds the user defined threshold.
System Monitor temperature-sensor Interrupt: The System Monitor
1
ALM[0]
R/TOW⁽²⁾
’0’ temperature-sensor alarm output interrupt occurs when the device
temperature exceeds the user defined threshold.
Over-Temperature alarm Interrupt: The Over-Temperature alarm
0
OT
R/TOW⁽²⁾
’0’ output interrupt occurs when the die temperature exceeds the factory
set limit of 125 degree celsius.
Notes:
1. TOW = Toggle On Write: Writing a ’1’ to a bit position within the register causes the corresponding bit position in the register to
toggle.
2. This interrupt signal is directly generated from SYSMON hard macro.
DS790 March 1, 2011
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17
Product Specification