DS790 Datasheet, PDF (24/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
2. If interrupt controller is present, i.e. C_INCLUDE_INTR = 1, do global enabling of interrupts by writing
0x8000_0000 to GIER.
3. Enable the operational interrupts by writing 0x0000_00FF to the IPIER.
4. Write 0x0000_0003 to Configuration Register 0. This configures the SYSMON hard macro with no averaging,
unipolar mode, event driven sampling, and selects channel 3 (V_P/V_N) for conversion.
5. Write 0x0000_3000 to Configuration Register 1. This configures the SYSMON hard macro in single channel
mode, all calibration disabled and all alarm outputs enabled.
6. Write 0x0000_2000 to Configuration Register 2. This configures the SYSMON hard macro to have ADCCLK =
DCLK/32.
7. Write 0x0000_0001 to the SYSMON Reset Register to reset the SYSMON hard macro. This step is required to put
the SYSMON hard macro in the reset state.
8. Read Status Register (SR) to reset EOC/EOS signal set by any previous conversions. After reading the Status
Register the EOC, EOS from IP core will be in reset state.
9. If interrupt controller is present, read IPISR to know the value set by any previous conversions. Assume that for
this application, the value read is 0x0000_003E.
10. Write 0x0000_003E to IPISR to toggle the bits which are ’1’ so that the new value of IPISR becomes 0x0000_0000.
11. Write 0x0000_0000 to the SYSMON Reset Register to bring the SYSMON hard macro out of reset. Once the
SYSMON hard macro comes out of reset, it will start its normal operation of data acquisition of the configured
channels.
12. Read SR, if conversion is completed then the EOC bit in SR will be set to ’1’. If the interrupt controller is present,
the EOC bit in the IPISR is also set to ’1’.
13. Read the converted value of channel 3 (V_P/V_N) from address C_BASEADDR + 0x20C.
Reference Documents
1. UG370, Virtex-6 FPGA System Monitor User Guide
2. AXI4 AMBA® AXI Protocol Version: 2.0 Specification
3. DS765, LogiCORE IP AXI Lite IPIF Data Sheet
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product documenta-
tion. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not
defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are
made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE^® Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
DS790 March 1, 2011
www.xilinx.com
24
Product Specification