DS790 Datasheet, PDF (7/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
Table 2: I/O Signal Descriptions (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
Description
P12 S_AXI_BREADY
AXI
I
-
Response ready: This signal indicates that the
master can accept the response information.
AXI Read Address Channel Signals
P13 ^{S_AXI_ARADDR[(C_S_AXI_}
AXI
ADDR_WIDTH - 1) : 0 ]
I
-
Read address: The read address bus gives the
address of a read transaction.
P14 S_AXI_ARVALID
Read address valid: This signal indicates, that
when HIGH, the read address and control
AXI
I
-
information is valid and will remain stable until the
address acknowledgement signal,
S_AXI_ARREADY, is High.
P15 S_AXI_ARREADY
Read address ready: This signal indicates that the
AXI
O
1 slave is ready to accept an address and associated
control signals.
AXI Read Data Channel Signals
S_AXI_RDATA[(C_S_AXI_
P16 _{DATA_WIDTH - 1) : 0]}
AXI
O
0 Read data
P17 S_AXI_RRESP[1 : 0]
Read response: This signal indicates the status of
the read transfer.
AXI
O
0 “00“ - OKAY (normal response)
“10“ - SLVERR (error condition)
“11“ - DECERR (not issued by core)
P18 S_AXI_RVALID
Read valid: This signal indicates that the required
AXI
O
0 read data is available and the read transfer can
complete.
P19 S_AXI_RREADY
Read ready: This signal indicates that the master
AXI
I
-
can accept the read data and response
information.
AXI Sysmon ADC Core Interface Signals
P20 VAUXP[15 : 0]
SYSMON
I
-
Positive auxiliary differential analog inputs.
P21 VAUXN[15 : 0]
SYSMON
I
-
Negative auxiliary differential analog inputs/
P22 CONVST
SYSMON
I
Convert Start input port is used to control the
-
sampling instant on the ADC input and only in
event-driven sampling mode. This port will be
auto-connected to ground internally, if not in use.
P23 ALARM[2:0]
SYSMON O
0 SYSMON hard macro alarm output signals.
DS790 March 1, 2011
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Product Specification