DS790 Datasheet, PDF (18/25 Pages) Xilinx, Inc – LogiCORE IP AXI SYSMON ADC

LogiCORE IP AXI SYSMON ADC (v2.00a)
IP Interrupt Enable Register (IPIER)
The IPIER register has an enable bit for each defined bit of the IPISR as shown in Figure 10 and described in
Table 12. All bits are cleared upon reset.
X-Ref Target - Figure 10
Undefined
OT JTAG
De-activeLOCKED _EOS ALM[1] OT
31
10 9 8 7 6 5 4 3 2 1 0
ALM[0]
EOC
ALM[0]
Deactive _JTAG
ALM[2]
MODIFIED
DS790_10
Figure 10: IP Interrupt Enable Register (IPIER)
Table 12: IP Interrupt Enable Register (IPIER) Description (C_BASEADDR + 0x68)
Bit(s)
Name
Access
Reset
Value
Description
31 - 10
Undefined
N/A
N/A
Undefined.
9
ALM[0] Deactive
R/W
ALM[0] Deactive Interrupt:
’0’
’0’ = Disabled
’1’ = Enabled
OT Deactive Interrupt:
8
OT Deactive
R/W
’0’
’0’ = Disabled
’1’ = Enabled
7
JTAG MODIFIED
R/W
JTAGMODIFIED Interrupt:
’0’
’0’ = Disabled
’1’ = Enabled
JTAGLOCKED Interrupt:
6
JTAG LOCKED
R/W
’0’
’0’ = Disabled
’1’ = Enabled
End of Conversion signal Interrupt:
5
EOC
R/W
’0’
’0’ = Disabled
’1’ = Enabled
End of Sequence Interrupt:
4
EOS
R/W
’0’
’0’ = Disabled
’1’ = Enabled
System Monitor V_CCAUX-sensor Interrupt:
3
ALM[2]
R/W
’0’
’0’ = Disabled
’1’ = Enabled
System Monitor V_CCINT-sensor Interrupt:
2
ALM[1]
R/W
’0’
’0’ = Disabled
’1’ = Enabled
System Monitor temperature-sensor Interrupt:
1
ALM[0]
R/W
’0’
’0’ = Disabled
’1’ = Enabled
Over-Temperature alarm Interrupt:
0
OT
R/W
’0’
’0’ = Disabled
’1’ = Enabled
DS790 March 1, 2011
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18
Product Specification