DS501 Datasheet, PDF (9/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 2: HARD_TEMAC I/O Signals (Cont’d)
Port
Signal Name
Interface I/O
Description
P11 ClientEmac0Txd(7:0)
V4EMACDST0 I Client transmit data
P12 ClientEmac0TxdVld
V4EMACDST0 I Client transmit data valid
P13 ClientEmac0TxdVldMsw
V4EMACDST0
I
Client transmit data valid most significant
word
P14 Emac0ClientTxAck
V4EMACDST0 O Client transmit acknowlege
P15 ClientEmac0TxUnderRun
V4EMACDST0 I Client tx under run
P16 Emac0ClientTxCollision
V4EMACDST0 O Client transmit collision indicator
P17 Emac0ClientTxRetransmit
V4EMACDST0 O Client retransmit indication
P18 ClientEmac0TxIfgDelay(7:0)
V4EMACDST0 I Client interframe gap delay for tx.
P19 ClientEmac0TxFirstByte
V4EMACDST0 I Client transmit first byte indicator
P20 Emac0ClientTxStats
V4EMACDST0 O Client transmit statistics
P21 Emac0ClientTxStatsVld
V4EMACDST0 O Client transmit statistics valid
P22 Emac0ClientTxStatsByteVld
V4EMACDST0 O Client transmit statistics byte valid
EMAC 0 Control Interface
P23 ClientEmac0PauseReq
V4EMACDST0 I Pause request
P24 ClientEmac0PauseVal(15:0)
V4EMACDST0 I Pause value
Emac 0 Clocks
P25 GTX_Clk_0
CLK0
I
P26 Rx_Client_Clk_0
V4EMACDST0 O Receive client clock
P27 Tx_Client_Clk_0
V4EMACDST0 O Transmit client clock
EMAC 0 MII Interface
P28 MII_TxD_0(3:0)
PHY0
O MII transmit data
P29 MII_Tx_En_0
PHY0
O MII transmit enable
P30 MII_Tx_Er_0
PHY0
O MII transmit error
P31 MII_RxD_0(3:0)
PHY0
I MII receive data
P32 MII_Rx_Dv_0
PHY0
I MII receive data valid
P33 MII_Rx_Er_0
PHY0
I MII receive error
P34 MII_Rx_Clk_0
PHY0
I MII receive clock
EMAC 0 MII & GMII Interface
P35 MII_Tx_Clk_0
PHY0
I MII and GMII transmit clock
EMAC 0 MII & GMII Interface
P36 GMII_TxD_0(7:0)
PHY0
O GMII transmit data
P37 GMII_Tx_En_0
PHY0
O GMII transmit enable
P38 GMII_Tx_Er_0
PHY0
O GMII transmit error
DS501 April 24, 2009
www.xilinx.com
9
Product Specification