DS501 Datasheet, PDF (19/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 8: EMAC Mode Configuration Register Bit Definitions
Bit
Name
Core
Access
Reset
Value
Description
0-1
Link
Speed
Read/Write
10 or 01 based on
C_PHY_TYPE
Link Speed: Determines link speed of operation:
00 = 10 Mb/s
01 = 100 Mb/s
10 = 1000 Mb/s
11 = N/A
2
RGMII
Read
0
RGMII mode enable: When set to “1”, RGMII is
enabled.
3
SGMII
Read
0 or 1 based on SGMII mode enable: When set to “1”, SGMII is
C_PHY_TYPE enabled.
1000
4
BaseX
Read
0
1000BaseX mode enable: When this bit is set to “1”,
the Ethernet MAC is configured in 1000Base-X mode.
5
Host
Enable
Read
1
Host Interface Enable: When this bit is set to “1”, the
host interface is used.
6 TX 16 Bit
Read
Transmit 16-bit Client Interface enable: When this bit
0
is set to “1”, the transmit data client interface is 16 bits
wide. When this bit is set to 0, the transmit data client
interface is 8 bits wide.
7 RX 16 Bit
Read
Receive 16-bit Client Interface enable: When this bit
0
is set to “1”, the receive data client interface is 16 bits
wide. When this bit is set to 0, the receive data client
interface is 8 bits wide.
8 - 31 Reserved
Read
0x0
Reserved: These bits are reserved for future definition
and will always return all zeros.
RGMII/SGMII Configuration Register (GMIC)
The RGMII/SGMII Configuration register provides configuration status for HARD_TEMAC as shown.
Figure Top x-ref 11
RGMII Link
Status
RGMII Link
Status
01
27 28 29 30 31
SGMII Link
Speed
Reserved
Figure 11: RGMII/SGMII Configuration Register (offset 0x3320)
RGMII HD
DS501_11_021507
DS501 April 24, 2009
www.xilinx.com
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Product Specification