DS501 Datasheet, PDF (17/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 6: Transmitter Configuration Register Bit Definitions
Bit
Name
Core ^Reset
Access Value
Description
Transmitter reset: When the bit is set to “1”, the HARD_TEMAC
0
TXRST Read/Write
0
receiver will be reset. The bit will then automatically revert “0”. Note
that this reset will also set all of the transmitter configuration
register to default values.
Jumbo frame enable: When this bit is set to “1”, the
1 TXJMBO Read/Write
1
HARD_TEMAC transmitter will send frames larger than the
IEEE802.3-2002 maximum legal length. When this bit is set to “0”,
the core will only send frames up to the specified maximum.
In-band FCS enable: When set to “1” the transmitter will expect
2
TXFCS Read/Write
0
the FCS field to be passed from the client. When set “0”, the
transmitter will append padding as required, and compute and
append the FCS.
3
TXEN Read/Write
1
Transmitter enable: If set to “1” the HARD_TEMAC transmitter is
enabled. Otherwise, the core transmitter is disabled.
4 TXVLAN Read/Write
1
VLAN enable: When set to “1” VLAN tagged frames will be sent by
the transmitter.
5
TXHD Read/Write
0
Half Duplex: If “1”, the transmitter will operate in half duplex mode.
Half Duplex is not supported so this bit should always be ’0’.
Interframe gap adjust enable: When set to "1", the transmitter
6
TXIFG Read/Write
0
uses the value of the IFGP register at the start of frame
transmission to adjust the Interframe Gap.
7 - 31 Reserved Read
0x0
Reserved: These bits are reserved for future definition and will
always return all zeros.
Flow Control Configuration (FCC)
The Flow Control Configuration register enables or disabled HARD_TEMAC flow control.
Figure Top x-ref 9
Reserved
RXFLO
012
31
TXFLO
Reserved
Figure 9: Flow Control Configuration Register (offset 0x3232C0)
DS501_09_021507
DS501 April 24, 2009
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Product Specification