DS501 Datasheet, PDF (8/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
HARD_TEMAC I/O Signals
The HARD_TEMAC core uses the transparent bus format to simplify generation of embedded systems
by greatly simplifying the connection of signals between the PLB_TEMAC and HARD_TEMAC cores.
This is the same technique that allows the EDK tools to automatically connect the PLB signals.
The ports on the PLB_TEMAC which connect to the HARD_TEMAC are grouped into a virtual bus
called V4EMACSRC. The corresponding signals on the HARD_TEMAC are grouped into two virtual
busses called V4EMACDST0 and V4EMACDST1 depending on which half of the HARD_TEMAC the
signals are used.
Most of what needs to be done to connect a PLB_TEMAC to 1/2 of a HARD_TEMAC is to designate
which PLB_TEMAC connects to which half of the HARD_TEMAC. This is done by assigning the
PLB_TEMAC virtual bus a name that matches the name assigned to the half of the HARD_TEMAC. An
example of how this is done is shown in the PLB_TEMAC specification. In the signal list below, those
signals that are assigned to the virtual bus are designated with an interface value of V4EMACDST0 and
V4EMACDST1.
When only using half of the HARD_TEMAC, the PLB_TEMAC must be connected to the half of the
HARD_TEMAC designated with the virtual bus V4EMACDST0. The half of the HARD_TEMAC
designated with the virtual bus V4EMACDST1 is only connected to a PLB_TEMAC when using both
halves of the HARD_TEMAC. When using only one PLB_TEMAC in a system the shared host signals
are unused and should be left unconnected. The inputs will automatically be tied high or low as
required.
When using both halves of the HARD_TEMAC, the two PLB_TEMACs must be connected together in
order to share the one host interface connection to the HARD_TEMAC. The PLB_TEMAC connected to
V4EMACDST0 will drive the host interface based on its own requests and those requests it receives
from the PLB_TEMAC connected to V4EMACDST1.
The external I/O signals for the HARD_TEMAC are listed in Table 2.
Table 2: HARD_TEMAC I/O Signals
Port
Signal Name
Interface I/O
Description
EMAC 0 Client Receive Interface
P1 Emac0ClientRxd(7:0)
V4EMACDST0 O Client receive Data
P2 Emac0ClientRxdVld
V4EMACDST0 O Client receive data valid
P3 Emac0ClientRxdVldMsw
V4EMACDST0
O
Client receive data valid on most
significant word
P4 Emac0ClientRxGoodFrame
V4EMACDST0 O Client valid receive frame indicator
P5 Emac0ClientRxBadFrame
V4EMACDST0 O Client invalid receive frame indicator
P6 Emac0ClientRxFrameDrop
V4EMACDST0 O Client receive frame dropped indication
P7 Emac0ClientRxdVreg6
V4EMACDST0 O Client receive data valid early registration
P8 Emac0ClientRxStats(6:0)
V4EMACDST0 O Client receive statistics
P9 Emac0ClientRxStatsVld
V4EMACDST0 O Client receive statistics valid indicator
P10 Emac0ClientRxStatsByteVld V4EMACDST0 O Client receive statistics byte valid
EMAC 0 Client Transmit Interface
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DS501 April 24, 2009
Product Specification