DS501 Datasheet, PDF (7/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
C_TEMAC0_PHYADDR and C_TEMAC1_PHYADDR
These values are used to control MII Management accesses to the internal PHY registers of EMAC 0
and EMAC 1 of the HARD_TEMAC core. An address of "00000" should not be used since this is a
broadcast addresses and all PHYs will respond to MII Management requests to this address possibly
causing contention. In most systems at least one and possibly more external PHYs will also be used. All
PHYs should all have unique PHY addresses.
C_IDELAYCTRL_LOC
When a PHY type of RGMII is selected, an IDELAY primitive is used to help align the receive data with
the receive clock. If both EMACs are used, one IDELAY primitive is used for each of the two EMACs.
When IDELAY primitives are used, a IDELAYCTRL primitive is also required. The IDELAYCTRL
primitive(s) must be located in the proper area in the silicon in order for it to be effective and this is
accomplished by adding constraints to the ucf-file. Additionally, a 200 MHz clock must be supplied to
the input RefClk which is used by the IDELAY and IDELAYCTRL primitives.
When two IDELAYCTRL primitives are used (when both EMACs are used in RGMII mode), LOC
constraints are required on each primitive. The FPGA Editor tool can be helpful to determine
IDELAYCTRL LOC coordinates for the user’s pinout.
The method for setting the LOC constraint(s) is to use the C_IDELAYCTRL_LOC parameter. This
parameter when properly set will generate constraints in the hard_temac core ucf file. Note that if the
LOC constraints are set in the system top-level ucf-file, then this parameter has no effect since the
constraints in the system top-level ucf-file override those in lower level ucf files.
The syntax of the parameter value is IDELAYCTRL_XNYM where N and M are coordinates and
multiple entries are concatenated by - (i.e, dash). The first value corresponds to EMAC0 and the second
value if present corresponds to EMAC1. The following is an example of how the parameter might be set
in the MHS file when both EMACs are used in RGMII mode. The X and Y values will be different for
each implementation. Please refer to the Virtex-4 User Guide for more information on selecting the
correct IDELAY Controller location.
PARAMETER C_IDELAYCTRL_LOC="IDELAYCTRL_X0Y0-IDELAYCTRL_X0Y1"
The quotes are optional.
C_RGMII_RX_CLK_IDELAY
When a PHY type of RGMII is selected, an IDELAY primitive is used to align the receive data with the
receive clock. The delay value must be provided for each IDELAY primitive used (one for each EMAC
used).
The method for setting the delay value is to use the C_RGMII_RX_CLK_DELAY parameter. This
parameter when properly set will generate constraints in the hard_temac core ucf file. Note that if the
delay constraints are set in the system top-level ucf file, then this parameter has no effect since the
constraints in the system top-level ucf file override those in lower level ucf files.
The syntax of the parameter value is N where N is the delay value for the receive clock and multiple
entries are concatenated by - (i.e, dash). The first value corresponds to EMAC0 and the second value if
present corresponds to EMAC1. The following is an example of how the parameter might be set in the
MHS file when both EMACs are used in RGMII mode.
PARAMETER C_RGMII_RX_DELAY="20-20"
The quotes are optional.
DS501 April 24, 2009
www.xilinx.com
7
Product Specification