DS501 Datasheet, PDF (16/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 5: Receiver Configuration Word 1 Register Bit Definitions
Bit Name
Core ^Reset
Access Value
Description
Receiver reset: When the bit is set to “1”, the HARD_TEMAC
0 RXRST Read/Write
0
transmitter will be reset. The bit will then automatically revert “0”.
Note that this reset will also set all of the Receiver configuration
registers to their default values.
Jumbo frame enable: When this bit is set to “1”, the
1
RXJMB
O
Read/Write
1
HARD_TEMAC receiver will accept frames larger than the
IEEE802.3-2002 maximum legal length. When this bit is set to “0”,
the core will only accept frames up to the specified maximum.
In-band FCS enable: When set to “1” the FCS field is passed to the
2 RXFCS Read/Write
1
client. Otherwise the FCS field is removed from the frame passed
to the client. In both cases, the HARD_TEMAC will verify the frame
FCS.
Receiver enable: If set to “1” the HARD_TEMAC receiver is
3
RXEN Read/Write
1
enabled. Otherwise, the HARD_TEMAC ignores any activity on the
RX port of the physical interface.
4 RXVLAN Read/Write
1
VLAN enable: When set to “1” VLAN tagged frames will be
accepted by the receiver.
5
RXHD Read/Write
0
Half Duplex: If “1”, the receiver will operate in half duplex mode.
Half Duplex is not supported so this bit should always be ’0’.
Length/type error check disable: When this bit is set to “1”, the
6
RXLT Read/Write
0
core will not perform the Length/type field error checks. When “0”.
normal operation.
7 - 15
Reserve
d
Read
0x0
Reserved: These bits are reserved for future definition and will
always return all zeros.
Pause frame MAC Source Address [47:32]: This address is used
16 -
31
ERXC1 Read/Write
0x0
by the HARD_TEMAC to match against the Destination Address of
any incoming flow control frames. It is also used as the Source
Address for any outbound flow control frames.
Transmitter Configuration (TXC)
The Transmitter Configuration provides operational features in the transmit side of the
HARD_TEMAC.
Figure Top x-ref 8
TXRST TXVLAN
TXFCS TXIFG
0123456
31
TXJMBO TXHD
TXEN
Reserved
Figure 8: Transmitter Configuration (offset 0x3280)
DS501_08_021507
16
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DS501 April 24, 2009
Product Specification