DS501 Datasheet, PDF (14/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
HARD_TEMAC Registers Definition
The HARD_TEMAC core registers are listed in Table 3. This description is appropriate for instances of
PLB_TEMAC that use the PLB_IPIF to interface to the registers within the HARD_TEMAC core.
Alternatively, these registers may be accessed through the DCR interface built into the processor block.
The HARD_TEMAC has seven configuration registers (RXC0, RXC1, TXC, FCC, EMCFG, GMIC, and
MC). These registers are accessed through the host interface and can be written to at any time. Both the
receiver and transmitter logic only respond to configuration changes during IFGs. The configurable
resets are the only exception, since the reset is immediate.
Address Filter Register access includes the address filter registers and the multicast address table
registers. The HARD_TEMAC has five address filter registers (UAW0, UAW1, MAW0, MAW1, and
AFM) with access through the host interface.
Some of the reset values of the HARD_TEMAC registers are determined by parameter settings of the
hard_temac core such as which PHY interface is to be used. Where this is the case, the variable reset
value will be identified.
Table 3: EMAC Core Registers
Register Name
Receive Configuration Word 0 (RXC0)
Receive Configuration Word 1 (RXC1)
Transmit Configuration (TXC)
Flow Control Configuration (FCC)
EMAC Mode Configuration (EMCFG)
RGMII / SGMII Configuration (GMIC)
Management Configuration (MC)
Unicast Address Word 0 (UAW0)
Unicast Address Word 1 (UAW1)
Multicast Address Word 0 (MAW0)
Multicast Address Word 1 (MAW1)
Address Filter Mode (AFM)
PLB ADDRESS
C_BASEADDR + 0x3200
C_BASEADDR + 0x3240
C_BASEADDR + 0x3280
C_BASEADDR + 0x32C0
C_BASEADDR + 0x3300
C_BASEADDR + 0x3320
C_BASEADDR + 0x3340
C_BASEADDR + 0x3380
C_BASEADDR + 0x3384
C_BASEADDR + 0x3388
C_BASEADDR + 0x338C
C_BASEADDR + 0x3390
Access
Read/Write
Read/Write
Read/Write
Read/Write
Read (29:0)
Read/Write (31:30)
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
14
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DS501 April 24, 2009
Product Specification