DS501 Datasheet, PDF (15/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
HARD_TEMAC Core Registers
Note: Receiver Configuration Word 0 (RXC0)
Word 0 of the Receiver Configuration holds the 32 least significant bits of pause frame MAC address.
Figure Top x-ref 6
0
31
Pause Frame MAC Address [31:0]
DS501_06_02150
Figure 6: Receiver Configuration Word 0 (offset 0x3200)
Table 4: Receiver Configuration Word 0 Register Bit Definitions
Bit Name
Core ^Reset
Access _Value
Description
Pause Frame MAC Address [31:0]: This address is used by the
0 - 31 ERXC0 Read/Write
0x0
HARD_TEMAC to match against the Destination Address of any
incoming flow control frames. It is also used as the Source Address
for any outbound flow control frames.
Receiver Configuration Word 1 (RXC1)
Word 1 of the Receiver Configuration holds the 16 most significant bits of pause frame MAC address
and several enable and disable bits as defined below.
Figure Top x-ref 7
RXRST RXVLAN
RXFCS RXLT
Pause Frame MAC Address[47:32]
0123456
16
31
RXJMBO RXHD
RXEN
Reserved
Figure 7: Receiver Configuration Word 1 (offset 3240)
DS501_07_021507
DS501 April 24, 2009
www.xilinx.com
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Product Specification