DS501 Datasheet, PDF (21/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
The PLB_TEMAC specification provides a simple example of C code that demonstrates writing and
reading of PHY registers using the MII Management interface.
Figure Top x-ref 12
CLOCK_DIVIDE
0
24 25 26
31
Reserved
MDIOEN
Figure 12: Management Configuration Register (offset 0x3340)
DS501_12_021507
Table 10: Management Configuration Register Bit Definitions
Bit
Name
Core ^Reset
Access Value
Description
0 - 24 Reserved
Read
0x0
Reserved: These bits are reserved for future definition and will
always return all zeros.
25
MDIO
Read /
Write
MII management enable: When this bit is “1”, the MII
1
management interface is used to access PHY devices. When this
bit is 0, the MII management interface is disabled and the MDIO
signal remain inactive.
26-31 CLK_DVD
Read /
Write
0x0
Clock Divide [5:0]: This value is used to derive the
EmacPhyMclkOut for external devices.
Unicast Address Register Word 0 (UAW0)
The Unicast Addresses Registers combine to provide a 48 bit ethernet station address. Word 0 provides
the low order 32 bits of the address while word 1 provides the high order 16 bits.
Figure Top x-ref 13
0
31
Unicast Address [31:0]
Figure 13: Unicast Address Register Word 0 (offset 0x3380)
Table 11: Unicast Address Register Word 0 Bit Definitions
Bit Name
Core ^Reset
Access _Value
Description
0 - 31 UAW0 Read/Write 0x0 MAC Unicast Address bits [31:0].
DS501_13_021507
DS501 April 24, 2009
www.xilinx.com
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Product Specification