DS501 Datasheet, PDF (18/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 7: Flow Control Configuration Register Bit Definitions
Bit
Name
Core ^Reset
Access Value
Description
0 Reserved Read/Write
0
Reserved: These bits are reserved for future definition and will
always return all zeros.
Transmit Flow Control Enable: When “0”, the request to transmit
1
TXFLO Read/Write
1
pause packets (write to TPP register) is ignored. When “1”.
requesting the transmit of a pause packet (write to TPP register)
will cause the HARD_TEMAC to send a flow control frame.
Receive Flow Control Enable: When “0”, received flow control
2 RXFLO Read/Write
1
frames will be passed to the client. When “1”, received flow control
frames will inhibit the HARD_TEMAC transmitter operation for a
short period of time as defined in IEEE802.3-2002.
3 - 31 Reserved Read
0x0
Reserved: These bits are reserved for future definition and will
always return all zeros.
EMAC Mode Configuration Register (EMCFG)
The EMAC Mode Configuration register provides configuration status of link speeds and
HARD_TEMAC PHY interface options as predefined at system build time based on PLB_TEMAC
parameters.
This release supports the MII, GMII, and SGMII interfaces. It does NOT support the RGMII or
1000BaseX interfaces.
Bits 5 - 7 refer to an internal interface between the PLB_TEMAC and the HARD_TEMAC and are fixed
and should not be needed by the user.
Bits 0 & 1 must be set to indicate the current operating link speed of the system. This may either be fixed
or may use auto negotiation.
Figure Top x-ref 10
1000BaseX
RGMII
TX16
01234567 8
31
Link Speed Host Enbl
SGMII
RX16
Reserved
Figure 10: EMAC Mode Configuration Register (offset 0x3300)
DS501_10_021507
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DS501 April 24, 2009
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