DS501 Datasheet, PDF (5/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Figure Top x-ref 3
FPGA Fabric
PLB_TEMAC
Host Sharing
Interface
HARD_TEMAC
Generic Host Interface
HARD_TEMAC
Rx Client Interface
HARD_TEMAC
Tx Client Interface
Host
Interface
PLB TEMAC
RX DRE
RX CSUM
Receive
Packet
FIFO
4K,8K,16K,
32K bytes)
Transmit
Packet
FIFO
4K,8K,16K,
32K bytes)
TX CSUM
PLB IPIF
Slave
Attachment
MIR
Interrupt
Controller
Master
Attachment
DMA
&
S/G
TX DRE
Figure 3: PLB TEMAC Block Diagram
DS501_03_021407
HARD_TEMAC Endianess
Note that the PLB_TEMAC is designed as a big endian device (bit 0 is the most significant bit and is
shown on the left of a group of bits).
The Hard TEMAC is designed as a little endian device (bit 0 is the least significant bit and is shown on
right of a group of bits).
The 8-bit GMII transmit and receive data interface to the external PHY is little endian (bit 7 is the most
significant bit and appears on the left of the bus). The MII management interface to the PHY is serial
with the most significant bit of a field being transmitted first.
HARD_TEMAC Design Parameters
To allow the user to generate a HARD_TEMAC that is tailored for their system, certain features are
parameterizable in the HARD_TEMAC design. This allows the user to have a design that only utilizes
the resources required by their system and runs at the best possible performance. The features that are
parameterizable in the Xilinx HARD_TEMAC design are shown in Figure 1
DS501 April 24, 2009
www.xilinx.com
5
Product Specification