DS501 Datasheet, PDF (12/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 2: HARD_TEMAC I/O Signals (Cont’d)
Port
Signal Name
Interface I/O
Description
P95 GMII_Tx_Clk_1
PHY1
O GMII transmit clock
P96 GMII_RxD_1(7:0)
PHY1
I GMII receive data
P97 GMII_Rx_Dv_1
PHY1
I GMII receive data valid
P98 GMII_Rx_Er_1
PHY1
I GMII receive error
P99 GMII_Rx_Clk_1
PHY1
I GMII receive clock
EMAC 1 SGMII Interface
P100 TxP_1
PHY1
O SGMII transmit positive
P101 TxN_1
PHY1
O SGMII transmit negative
P102 RxP_1
PHY1
I SGMII receive positive
P103 RxN_1
PHY1
I SGMII receive negative
EMAC 1 RGMII Interface
P104 RGMII_TxD_1(3:0)
PHY1
O Reserved for future use
P105 RGMII_Tx_Ctl_1
PHY1
O Reserved for future use
P106 RGMII_TxC_1
PHY1
O Reserved for future use
P107 RGMII_RxD_1(3:0)
PHY1
I Reserved for future use
P108 RGMII_Rx_Ctl_1
PHY1
I Reserved for future use
P109 RGMII_RxC_0
PHY1
I Reserved for future use
EMAC 1 MDIO Interface
P110 MdC_1
PHY1
O MII Management Clock
P111 MdIO_1
PHY1
I/O MII Management Data
P112 EMAC1ClientAnInterrupt
V4EMACDST1 O Auto negotiation complete interrupt
Host Interface
P113 HostOpCode(1:0)
V4EMACDST0 I Host read / write indication
P114 HostReq
V4EMACDST0 I Host IF request
P115 HostMiimSel
V4EMACDST0 I Host select for MII management
P116 HostAddr(9:0)
V4EMACDST0 I Host address
P117 HostWrData(31:0)
V4EMACDST0 I Data written through Host IF
P118 HostMiimRdy
V4EMACDST0 O MII management / host IF is ready
P119 HostRdData(31:0)
V4EMACDST0 O Data read through Host IF
P120 HostEmac1Sel
V4EMACDST0 I Host select for EMAC no. 1
P121 HostClk
V4EMACDST0 I Host clock (1 - 100 MHz)
SGMII MGT Clocks
P122 MGTClk_P
CLK
I MGT clock positive
P123 MGTClk_N
CLK
I MGT clock negative
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DS501 April 24, 2009
Product Specification