DS501 Datasheet, PDF (24/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 15: Address Filter Mode Register Bit Definitions
Bit
Name
Core ^Reset
Access Value
Description
0
EPRM
Read /
Write
Promiscuous Mode Enable: When this bit is set to “1”, the
1
Address Filter Block is disable. When this bit is set to 0, the
Address Filter Block is enabled.
1-31 Reserved
Read
0x0
Reserved: These bits are reserved for future definition and will
always return all zeros.
Design Implementation
Design Tools
The HARD_TEMAC design is implemented using VHDL code.
To see the synthesis tool used for this device, go to Tools. The NGC netlist output is then input to the
Xilinx Foundation tool suite for device implementation.
Target Technology
The target technology is an FPGA listed in EDK Supported Device Families.
Device Utilization and Performance Benchmarks
Since the HARD_TEMAC is a VHDL wrapper around a hard silicon component, this core does not
utilize FPGA fabric resources.
Specification Exceptions
The HARD_TEMAC design currently has no exceptions to the mandatory IEEE Std. 802.3 MII interface
requirements.
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
24
www.xilinx.com
DS501 April 24, 2009
Product Specification