DS501 Datasheet, PDF (3/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
The Hard TEMAC silicon component functionality consumes no FPGA programmable resources since
the Hard TEMAC is built into the silicon of each Virtex-4 FX FPGA. Please refer to the HARD_TEMAC
silicon component specification for more details.
Figure 1 is a block diagram of the Hard TEMAC and the PowerPC processor Silicon Components.
Figure Top x-ref 1
Processor Block
ISOCM
Control
Physical
Interface
EMAC
Block
Client Data
Interface
FPGA Auxiliary
Processor Port
IS-PLB Port
DS-PLB Port
DCR Interface
APU
Control
APU ^ISOCM
DCR
Control
Test ^Reset
and
Control
ISPLB
PPC405
DSPLB _Processor
DCR
DSOCM
DSOCM
Control
EMAC
DCR
Bus
Host
Interface
EMAC
Client
Statistics
Interface
Generic
Host Bus
Client
Statistics
Interface
Physical Client Data
Interface Interface
DS501_01_021407
Figure 1: Hard TEMAC and PowerPC Processor Controller Silicon Components Block Diagram
DS501 April 24, 2009
www.xilinx.com
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Product Specification