DS501 Datasheet, PDF (11/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 2: HARD_TEMAC I/O Signals (Cont’d)
Port
Signal Name
Interface I/O
Description
P67 ClientEmac1Txd(7:0)
V4EMACDST1 I Client transmit data
P68 ClientEmac1TxdVld
V4EMACDST1 I Client transmit data valid
P69 ClientEmac1TxdVldMsw
V4EMACDST1
I
Client transmit data valid most significant
word
P70 Emac1ClientTxAck
V4EMACDST1 O Client transmit acknowlege
P71 ClientEmac1TxUnderRun
V4EMACDST1 I Client tx under run
P72 Emac1ClientTxCollision
V4EMACDST1 O Client transmit collision indicator
P73 Emac1ClientTxRetransmit
V4EMACDST1 O Client retransmit indication
P74 ClientEmac1TxIfgDelay(7:0)
V4EMACDST1 I Client interframe gap delay for tx.
P75 ClientEmac1TxFirstByte
V4EMACDST1 I Client transmit first byte indicator
P76 Emac1ClientTxStats
V4EMACDST1 O Client transmit statistics
P77 Emac1ClientTxStatsVld
V4EMACDST1 O Client transmit statistics valid
P78 Emac1ClientTxStatsByteVld
V4EMACDST1 O Client transmit statistics byte valid
EMAC 1 Control Interface
P79 ClientEmac1PauseReq
V4EMACDST1 I Pause request
P80 ClientEmac1PauseVal(15:0)
V4EMACDST1 I Pause value
Emac 1 Clocks
P81 GTX_Clk_1
CLK1
I
P82 Rx_Client_Clk_0
V4EMACDST1 O Receive client clock
P83 Tx_Client_Clk_0
V4EMACDST1 O Transmit client clock
EMAC 1 MII Interface
P84 MII_TxD_1(3:0)
PHY1
O MII transmit data
P85 MII_Tx_En_1
PHY1
O MII transmit enable
P86 MII_Tx_Er_1
PHY1
O MII transmit error
P87 MII_RxD_1(3:0)
PHY1
I MII receive data
P88 MII_Rx_Dv_1
PHY1
I MII receive data valid
P89 MII_Rx_Er_1
PHY1
I MII receive error
P90 MII_Rx_Clk_1
PHY1
I MII receive clock
EMAC 1 MII & GMII Interface
P91 MII_Tx_Clk_1
PHY1
I MII and GMII transmit clock
EMAC 1 GMII Interface
P92 GMII_TxD_1(7:0)
PHY1
O GMII transmit data
P93 GMII_Tx_En_1
PHY1
O GMII transmit enable
P94 GMII_Tx_Er_1
PHY1
O GMII transmit error
DS501 April 24, 2009
www.xilinx.com
11
Product Specification