DS501 Datasheet, PDF (1/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

DS501 April 24, 2009
HARD Tri-Mode Ethernet MAC
(TEMAC) (v3.00b)
Product Specification
Introduction
This document provides the design specification for the
HARD_TEMAC (Tri-mode Ethernet Media Access
Controller) soft core. Tri-mode indicates that this core
may transmit and receive data at three rates, 10, 100, or
1000 Megabits per second (Mb/s).
The HARD_TEMAC described in this document has
been designed incorporating the applicable features
described in IEEE Std. 802.3-2002. Differences between
that specification and the Xilinx HARD_TEMAC
implementation are highlighted and explained in the
<RD Red>Specification Exceptions section.
The HARD_TEMAC is an intellectual property (IP) soft
core designed for implementation in a Virtex^®-4 FX
FPGA. The HARD_TEMAC soft core provides a
wrapper around the Hard TEMAC component
implemented in the Virtex-4 FX FPGA silicon to allow it
to be used in an embedded system with the Embedded
Development Kit (EDK) tools. The Virtex-4 FX FPGA
Hard TEMAC silicon component has a detailed users
guide which should be used to supplement this
document. See the "Reference Documents" section of
this document.
The HARD_TEMAC v3.00b core is designed to be used
with the PLB_TEMAC v3.00a core to couple the
TEMAC to the PowerPC^® controller via the Processor
Local Bus (PLB).
Two instances of the PLB_TEMAC are required if both
halves of the Hard TEMAC are to be used with the PLB
bus. Those Virtex-4 FX FPGAs which have two
PowerPC controllers have a second Hard TEMAC
available. Each half of a Hard TEMAC to be used with
the PLB requires a separate instance of the
PLB_TEMAC.
LogiCORE™ Facts
Core Specifics
Supported Device
Family
See EDK Supported Device
Families.
Version of Core
HARD_TEMAC
v3.00b
Resources Used
Min
Max
Total Core I/O
332
332
Core FPGA IOBs
4
48
LUTs
0
0
FFs
0
0
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Reference Designs
None
Design Tool Requirements
Xilinx Implementation
Tools
Verification
Simulation
See Tools for requirements.
Synthesis
Support
Provided by Xilinx, Inc.
© 2005-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS501 April 24, 2009
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Product Specification