DS501 Datasheet, PDF (20/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Table 9: RGMII/SGMII Configuration Register Bit Definitions
Bit
Name
Core ^Reset
Access Value
Description
0-1
SGMII Link
Speed
Read
SGMII Link Speed: Valid in SGMII mode configuration only. This
displays the SGMII speed information, as received by
TX_CONFIG_REG[11:10] in the PCS/PMA register. This 2-bit
vector is defined with the following values:
00
00 = 10 Mb/s
01 = 100 Mb/s
10 = 1000 Mb/s
11 = N/A
2 -27 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will
always return all zeros.
28 - RGMII Link
29
Speed
Read
RGMII Link Speed: Valid in RGMII mode configuration only.
Link information from PHY to HARD_TEMAC as encoded by
GMII_RX_DV and GMII_RX_ER during the IFG. This 2-bit
vector is defined with the following values:
00
00 = 10 Mb/s
01 = 100 Mb/s
10 = 1000 Mb/s
11 = N/A
30
RGMII Half
Duplex
Read
RGMII Half Duplex: Valid in RGMII mode configuration only.
When this bit is “1”, the HARD_TEMAC operates in half-duplex
0
mode. When this bit is “0”, the core operates in full-duplex mode.
This displays the duplex information from PHY to
HARD_TEMAC, encoded by GMII_RX_DV and GMII_RX_ER
during the IFG.
31
RGMII Link
Status
Read
RGMII Link Status: Valid in RGMII mode configuration only.
When this bit is “1”, the link is up. When this bit is “0”, the link is
0
down. This displays the link information from PHY to
HARD_TEMAC, encoded by GMII_RX_DV and GMII_RX_ER
during the IFG.
Management Configuration Register (MC)
The Management Configuration Register provides control for the HARD_TEMAC PHY MII
management (MDIO) interface. The MDIO interface supplies a clock to the external devices,
EMAC#PHYMCLKOUT. This clock is derived from the HARD_TEMAC HOSTCLK signal which is
connected to the PLB_CLK inside the PLB_TEMAC core using the value in the Clock Divide[5:0]
configuration register. The frequency of the MDIO clock is given by the following equation:
f_MDC = ₍---1----+------C----l--o---c--^f-k^H----^O_D----^S-i--^T_v---^C_i--d-^L--^K-e--[--5---:--0---]--₎----_×-----2-
To comply with the IEEE 802.3-2002 specification for this interface, the frequency of
EMAC#PHYMCLKOUT should not exceed 2.5 MHz. To prevent EMAC#PHYMCLKOUT from being
out of specification, the Clock Divide[5:0] value powers up at 000000. While this value is in the register,
it is impossible to enable the MDIO interface. Given this, even if the user has enabled the MDIO
interface by setting bit 25 of this register, the MDIO port will still be disabled until a non-zero value has
been written into the clock divide bits.
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DS501 April 24, 2009
Product Specification