DS501 Datasheet, PDF (22/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Unicast Address Register Word 1 (UAW1)
The Unicast Addresses Registers combine to provide a 48 bit ethernet station address. Word 0 provides
the low order 32 bits of the address while word 1 provides the high order 16 bits.
Figure Top x-ref 14
0
15 16
31
Reserved
Unicast Address [47:32
Figure 14: Unicast Address Register Word 1 (offset 0x3384)
DS501_14_021507
Table 12: Unicast Address Register Word 1 Bit Definitions
Bit
Name
Core ^Reset
Access _Value
Description
0-15 Reserved
Read
0x0
Reserved: These bits are reserved for future definition and
will always return all zeros
16-31
UAW1
Read/Write 0x0 MAC Unicast Address bits [47:32].
Multicast Address Register Word 0 (MAW0)
The Multicast Addresses Registers combine to provide a 48 bit ethernet addresses to store in content
addressable memory (CAM). Word 0 provides the low order 32 bits of the address while word 1
provides the high order 16 bits. Word also provides CAM register addresses and the read or write
control signal. The PLB_TEMAC specification provides a simple example of C code that demonstrates
writing and reading the multicast address CAM.
Figure Top x-ref 15
0
31
Unicast Address [31:0
Figure 15: Multicast Address Register Word 0 (offset 0x3388)
DS501_15_021507
Table 13: Unicast Address Register Word 1 Bit Definitions
Bit
Name
Core ^Reset
Access Value
Description
0-15 Reserved
Read
0x0
Reserved: These bits are reserved for future definition and
will always return all zeros
16-31
UAW1
Read/Write 0x0 MAC Unicast Address bits [47:32].
Multicast Address Register Word 1 (MAW1)
The Multicast Addresses Registers combine to provide a 48 bit ethernet addresses to store in content
addressable memory (CAM). Word 0 provides the low order 32 bits of the address while word 1
provides the high order 16 bits. Word also provides CAM register addresses and the read or write
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DS501 April 24, 2009
Product Specification