DS501 Datasheet, PDF (23/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
control signal. The PLB_TEMAC specification provides a simple example of C code that demonstrates
writing and reading the multicast address CAM.
Figure Top x-ref 16
CAMRNW
CAM ADDR
0
8
14 15 16
31
Reserved
Reserved
Multicast address [47:32]
Figure 15: Multicast Address Register Word 1 (offset 0x338C)
DS501_11_021507
Table 14: Multicast Address Register Word 1 Bit Definitions
Bit
Name
Core Reset
Access _Value
Description
0-7
Reserved Read/Write
0x0
Reserved: These bits are reserved for future definition and will
always return all zeros.
CAMRNW: CAM read, not write used to control the reading and
8
CAMRNW Read/Write
0
writing of Multicast addresses into the content addressable
memory registers.
9-13
Reserved Read/Write
0x0
Reserved: These bits are reserved for future definition and will
always return all zeros.
CAMADDR: This two bit vector is used to choose the CAM
Register to access.
00 = CAM Register 0
14-15 CAMADDR Read/Write 0x0 _{01 = CAM Register 1}
10 = CAM Register 2
11 = CAM Register 3
16-31 MAW0 Read/Write 0x0 MAC Multicast Address bits [47:32].
Address Filter Mode Register (AFM)
This is a one bit register used to enable or disable address filtering. When promiscuous mode is
enabled, all inbound frames will be received and processed. When promiscuous mode is disabled, all
inbound frames will be filtered by their respective destination addresses subject the present unicast,
multicast, and broadcast addresses programmed into the MAC.
Figure Top x-ref 17
01
31
EPRM
Reserved
Figure 16: Address Filter Mode Register (offset 0x3390)
DS501_17_021507
DS501 April 24, 2009
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Product Specification