DS501 Datasheet, PDF (4/25 Pages) Xilinx, Inc – HARD Tri-Mode Ethernet MAC

HARD Tri-Mode Ethernet MAC (TEMAC) (v3.00b)
Figure 2 is a detailed block diagram of the Hard TEMAC. This shows two EMACs with a unified Host
interface for access to the configuration registers of both EMACs. The Host interface can be accessed
either from a generic signal interface or from a DCR connection which is part of the hard silicon design
of the PowerPC controller and the Hard TEMAC. Each EMAC has its own set of Client, PHY, PHY
Management, and statistics interfaces.
Figure Top x-ref 2
ClientTx1/Rx1
StatsIP1
Rx Stats MUX1 Tx Stats MUX1
EMAC1
Tx1/Rx1
To PowerPC 405 block
Generic Host Bus
DCR Bus
DCR
Bridge
Host Interface
PHY
ClientTx0/Rx0
EMAC0
Tx0/Rx0
Ethernet MAC _{Rx Stats MUX0 Tx Stats MUX0}
Block
FPGA Fabric
StatsIP0
DS501_02
Figure 2: Detailed Block Diagram of the Hard TEMAC Silicon Component
PLB_TEMAC Core
The PLB_TEMAC provides access to the HARD_TEMAC host interface from the PLB. The DCR
Interface, built in the silicon, is not supported.
The PLB_TEMAC enables memory mapped access to registers and memory mapped or DMA access to
packet FIFOs which in turn interface to the Client transmit and receive interfaces of the
HARD_TEMAC to support transmission and reception of Ethernet frames. The PLB_TEMAC is
comprised of several blocks as shown in Figure 3 for a PLB_TEMAC with DMA.
4
www.xilinx.com
DS501 April 24, 2009
Product Specification