DS730 Datasheet, PDF (8/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
pCore Register Set
The pCore interface provides a memory mapped interface for the programmable registers within the core, which
are defined in Table 1, all registers default to 0x00000000 on Power-on/Reset.
Table 1: Video DMA pCore Memory Mapped Register Set
Address (hex)
Register Name
Access Type
Description
BASEADDR +
0x0000
VDMA Control
R/W
General Control Register
31
Reserved
SW Write DMA Reset
30
Clear Write DMA Command and
Flush Write Data.
SW Read DMA Reset
29
Clear Read DMA Command and
Flush Read Data.
28
SW Write FIFO Flush
27
SW Read FIFO Flush
26
Reserved
Read HW Lockout
1=Disable VDMA Read Command
Hardware from writing to
25
Command Interface. All
commands from the VDMA Read
Command Interface will be
ignored.
Write HW Lockout
1=Disable VDMA Write Command
Hardware from writing to
24
Command Interface. All
commands from the VDMA Write
Command Interface will be
ignored.
20:23
Read Frame Store Pointer
When Circular Buffer Enable = 0,
the Frame Store Start Address
reference number stored here will
force the VDMA to place
transactions to/from this Start
Address.
Ignored with Circular Buffer Enable
= 1.
16:19
Write Frame Store Pointer
When Circular Buffer Enable = 0,
the Frame Store Start Address
reference number stored here will
force the VDMA to place
transactions to/from this Start
Address.
Ignored with Circular Buffer Enable
= 1.
DS730 September 21, 2010
www.xilinx.com
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Product Specification