DS730 Datasheet, PDF (24/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
Table 6: Processor Local Bus (PLB) v4.6 Signals (Cont’d)
Name
Direction
Description
PLB_UABus[0:31]
In
PLB Upper Address Bus
PLB_BusLock
In
PLB Bus Lock
PLB_LockErr
In
PLB Lock Error
PLB_TAttribute[0:15]
In
PLB Attribute
PLB_RdPrim
In
PLB Read Primary
PLB_WrPrim
In
PLB Write Primary
PLB_RDPendPri[0:1]
In
PLB Read Pending on Primary
PLB_WrPendPri[0:1]
In
PLB Write Pending on Primary
PLB_RdPendReq
In
PLB Read Pending Request
PLB_WrPendReq
In
PLB Write Pending Request
Sl_addAck
Out
Slave Address Acknowledge
Sl_SSize[0:1]
Out
Slave Data Bus Size
Sl_wait
Out
Slave Wait Indicator
Sl_rearbitrate
Out
Slave Rearbitrate Bus indicator
Sl_wrDAck
Out
Slave Write Data Acknowledge
Sl_wrComp
Out
Slave Write Transfer Complete indicator
Sl_wrBTerm
Out
Slave Terminate Write Burst Transfer
Sl_rdDBus[0:C_SPLB_DWIDTH-1]
Out
Slave Read Data Bus
Sl_rdWdAddr[0:3]
Out
Slave Read Word Address
Sl_rdDAck
Out
Slave Read Data Acknowledge
Sl_rdComp
Out
Slave Read Transfer Complete indicator
Sl_rdBTerm
Out
Slave Terminate Read Burst Transfer
Sl_MBusy[0:C_SPLB_NUM_MASTERS-1]
Out
Slave Busy indicator
Sl_MrdErr[0:C_SPLB_NUM_MASTERS-1]
Out
Slave Read Error indicator
Sl_MwrErr[0:C_SPLB_NUM_MASTERS-1]
Out
Slave Write Error indicator
Sl_MIRQ[0:C_SPLB_NUM_MASTERS-1]
Out
Slave Interrupt
IP2INTC_Irpt
Out
Interrupt Signal
DS730 September 21, 2010
www.xilinx.com
24
Product Specification