DS730 Datasheet, PDF (29/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
Table 9: Control, Interrupt and Status Signals (Cont’d)
Name
Direction
Description
intr_wd_done
Out
Write DMA Done Interrupt
intr_rd_frame_count
Out
Read Frame Count Interrupt
intr_rd_delay_count
Out
Read Delay Count Interrupt
intr_rd_frame_repeat
Out
Read Frame Repeat Interrupt
intr_rd_frame_skip
Out
Read Frame Skip Interrupt
intr_rd_done
Out
Read DMA Done Interrupt
intr_err_address
Out
Address Error Interrupt
intr_err_write_busy
Out
Write Busy Error Interrupt
intr_err_wd_fifo
Out
Write FIFO Error Interrupt
intr_err_wcmd_fifo
Out
Write Cmd FIFO Error Interrupt
intr_err_rd_fifo
Out
Read FIFO Error Interrupt
intr_err_rcmd_fifo
Out
Read Cmd FIFO Error Interrupt
stat_busy
Out
VDMA Busy
stat_cmd_almost_full
Out
Cmd FIFO Almost Full
stat_cmd_full
Out
Cmd FIFO Full
stat_wd_full
Out
Write FIFO Full
stat_wd_almost_full
Out
Write FIFO Almost Full
stat_rd_empty
Out
Read FIFO Empty
stat_rd_almost_emtpy
Out
Read FIFO Almost Empty
stat_cmd_we
Out
Cmd FIFO Write Enable
stat_wd_we
Out
Write FIFO Write Enable
stat_rd_re
Out
Read FIFO Read Enable
stat_last_fstore [3:0]
Out
Max Valid Frame Store
stat_curr_wd_fstore [3:0]
Out
Current Write Frame Store
stat_curr_rd_fstore [3:0]
Out
Current Read Frame Store
stat_wd_frame_count [7:0]
Out
Write Frame Counter Value
stat_rd_frame_count [7:0]
Out
Read Frame Counter Value
stat_wd_delay_count [7:0]
Out
Write Delay Count Value
stat_rd_delay_count [7:0]
Out
Read Delay Count Value
stat_version [31:0]
Out
VDMA Version Number
Note: The Control, Interrupt, and Status Signals in Table 9 are the same as the bits in the pCore Memory Mapped Register Set.
See Table 1 for more information on these signals.
DS730 September 21, 2010
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Product Specification