DS730 Datasheet, PDF (38/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
If the "Bus Interface" is set to VDMA and the "DMA Mode" is set to Read_Only or Write_Only, the fsync signal is
used for Fsync Synchronization. If the "Bus Interface is set to VDMA and the "DMA Mode" is set to Read/Write, the
rd_fsync and wd_fsync signals are used to separately control the read and write sides respectively. If the "Bus
Interface" is set to XSVI, the xsvi_rd_vsync_in and xsvi_wd_vsync_in signals are used to control the read
and write sides respectively.
Non-Aligned Address Commands
The VFBC requires that all command addresses conform to a 128-byte address boundary. The Video DMA was
designed to allow the reads and writes that do not conform to this 128-byte address boundary. When the “Allow
Non-Aligned Transfers” option is selected, the Video DMA is generated with additional resources that handle the
work of converting between a non-aligned transfer on the Video DMA side and an aligned transfer on the VFBC
side. This is done by rounding the non-aligned memory address down to the nearest 128-byte address boundary
before it is written to the VFBC. Since extra data must be padded to the front and end of each transferred line, the
“horizontal length” value must also be increased appropriately.
For write commands, the Video DMA pads the front and end of each line of the transfer so that each line conforms
to the 128-byte boundaries. Figure 12 illustrates a non-aligned write operation. The command on the vdma_cmd
port is offset by 0x04 bytes. The Video DMA rounds the address down to the nearest 128-byte boundary and sends
that value to the VFBC. Since extra data must be padded to the front and end of each line to conform to the 128-byte
boundaries, the “horizontal length” portion of the VFBC command must also be adjusted accordingly. The data bus
for this example is 32-bits (4 bytes) wide. As a result, the Video DMA must pad one transfer to the VFBC for the
transfer to conform to the VFBC 128-byte address boundaries.
X-Ref Target - Figure 12
Figure 12: Non-Aligned Write Operation (Address Non-Alignment = 0x04)
For read commands, the Video DMA crops the data coming from the VFBC to extract only the portion of the data
that the Video DMA is interested in keeping. Figure 13 is an example of a non-aligned read operation. In this
example the address in the Video DMA read command is of offset by 0x1C bytes. The data bus for this example is
32-bits (4 bytes) wide. The Video DMA rounds the address written to the VFBC down to the nearest 128-byte
boundary. Once the transfer begins, the Video DMA crops the first 7 transfers to account for the address non-
alignment of 0x1C (7*4bytes = 28 bytes).
X-Ref Target - Figure 13
Figure 13: Non-Aligned Read Operation (Address Non-Alignment = 0x1C)
DS730 September 21, 2010
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Product Specification