DS730 Datasheet, PDF (12/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
Table 1: Video DMA pCore Memory Mapped Register Set (Cont’d)
Address (hex)
Register Name
Access Type
Description
BASEADDR + Control Write Frame Size
R/W
Horizontal Size and Vertical Size of Each Write
0x0020
FIFO Frame
28:31 Reserved
16:27
VDMA Write Vsize
The write vertical size in lines
starting from line 0.
12:15 Reserved
VDMA Write HSize
0:11 _{The horizontal size in number of}
data writes.
BASEADDR +
0x0024
Control Write Stride
R/W
Stride (Line Increment) of each Write FIFO
Frame
20:31 Reserved
16:19
Write Frame Delay
The number of frame stores the
write VDMA should be behind the
locked Read DMA.
Used only if the “Write Gen-Lock
Mode” parameter is set to “SLAVE”
and the circular buffer is enabled.
12:15 Reserved
VDMA Write Stride
0:11 The stride in number of data
elements of DATA WIDTH size.
BASEADDR + Control Read Frame Size
R/W
Horizontal Size and Vertical Size of each Read
0x0028
FIFO Frame
28:31 Reserved
16:27
VDMA Read Vsize
The read vertical size in lines
starting from line 0.
12:15 Reserved
VDMA Read HSize
0:11 _{The horizontal size in number of}
data reads.
BASEADDR +
0x002c
Control Read Stride
R/W
Stride (Line Increment) of each Read FIFO
Frame
20:31 Reserved
16:19
Read Frame Delay
The number of frame stores the
read VDMA should be behind the
locked Write DMA.
Used only if the “Read Gen-Lock
Mode” parameter is set to “SLAVE”
and the circular buffer is enabled.
12:15 Reserved
VDMA Read Stride. The stride in
0:11 number of data elements of DATA
WIDTH size.
DS730 September 21, 2010
www.xilinx.com
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Product Specification