DS730 Datasheet, PDF (30/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

LogiCORE IP Video Direct Memory Access v1.1
Video DMA Control and Timing
The Video DMA can be operated in a number of different modes. The modes are the same for “Read Only”, “Write
Only”, and “Read/Write” operations.
Command Format
All VDMA operations involve writing a command to the VFBC cmd port. The VFBC commands consist of 4-word
packets. Table 10 shows the command packet data structure.
Table 10: Command Packet Data Structure
Command Packet
Command Word 0
Command Word 1
Command Word 2 Command Word 3
31:15
14:0
31
30:0
31:24
Reserved X_Size⁽¹⁾ Write_ NotRead Start Address⁽¹⁾ Reserved
23:0
Y_Size
31:24
23:0
Reserved Stride⁽¹⁾
1. The X_Size, Start Address and Stride must be aligned to a 32-word boundary. These values must be a multiple of 128 bytes and
require that bits [6:0] be 0.
• Command Word 0 – Includes the X Size of the transfer, which is the number of consecutive linear bytes of the
transaction per line.
• Command Word 1– Includes the direction of the transfer and the start address. Bit 31, or Write_NotRead,
denotes a write transaction if high and a read transaction if low. Bits 30:0 are the physical memory byte start
address, which is the start address of the transfer.
• Command Word 2 –Includes the Y Size of the transfer, which is the number of lines of the transfer minus one.
• Command Word 3 – Includes the Stride of the transfer, which is the number of bytes to skip between the start
of each line of the transfer. This is the line length (in bytes) of the 2D storage in external memory.
Basic Read Operation
When configured in “Read Only” mode, the Video DMA can perform read operations in a number of different
ways, all of which follow the same basic format. The basic read operation of the Video DMA is as follows:
1. The Video DMA sends a “read command” to the VFBC. This command tells the VFBC how much data to read
and from where to read the data.
2. VFBC signals that it has data ready to be transferred.
3. The Video DMA inputs the data on the vfbc_rd port from the VFBC.
4. The Video DMA then outputs the data on the vdma_rd port.
The Video DMA uses FIFO flow control signals on the vfbc_rd and vdma_rd ports to control the flow of data.
More detailed descriptions of the different read operations can be found in the sections that follow.
DS730 September 21, 2010
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Product Specification