DS730 Datasheet, PDF (1/46 Pages) Xilinx, Inc – LogiCORE IP Video Direct

DS730 September 21, 2010
LogiCORE IP Video Direct
Memory Access v1.1
Product Specification
Introduction
The Xilinx Video Direct Memory Access (Video DMA)
LogiCORE™ IP allows video cores to access external
memory via the Video Frame Buffer Controller (VFBC)
port on the Multi-Port Memory Controller (MPMC).
The Video DMA is highly programmable through
registers coupled with a wide range of interrupts,
allowing for easy control of the various features of the
core. The integration with the MicroBlaze™ Soft
Processor for in-system control of the block in real-time
allows designers an easy path to integrate DMA
functionality for video data accesses.
Features
• Programmable register control
• Selectable processor interface
• EDK pCore
• General Purpose Processor
• Selectable Master/Slave Gen-Lock Mode
• Selectable data interface
• VDMA FIFO interface
• Xilinx Streaming Video Interface (XSVI)
• Configurable Read, Write, or Read/Write DMA
mode
• Programmable data width -8, -16, -32 or -64
• Seamless integration with Video Frame Buffer
Controller
• PLB46 support for interrupts and status register
access
• Support for up to 16 buffer addresses
• Support for non-aligned transfers
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family ⁽¹⁾
Spartan^®-3A DSP, Spartan-6, Virtex^®-5, Virtex-6
Supported User
Interfaces
General Processor Interface, EDK PLB 4.6
Resources ⁽²⁾
Frequency
Configuration
LUTs
FFs
DSP Block
Slices RAMs⁽³⁾
Max.
Freq. ⁽⁴⁾
Write_Only,
pCore IF,
1048 1617 0
0
225
5 Frame Stores
Read_Only,
pCore IF,
3 Frame Stores, 1177 1588 0
0
225
Non-Aligned
Transfers
Read/Write,
pCore IF,
1240 1678 0
0
225
3 Frame Stores
Provided with Core
Documentation
Product Specification
Design Files
Netlist, EDK pCore
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
Not Provided
Simulation
Model
Design Entry
Tools
Simulation
Not Provided
Tested Design Tools
ISE^® 12.3
XPS 12.3
ModelSim v6.5c
ISE Simulator 12.3
Synthesis Tools
Support
ISE XST 12.3
Provided by Xilinx, Inc.
1. For a complete listing of supported devices, see the release notes
for this core.
2. Resources listed here are for Virtex-6® devices. For more complete
device performance numbers, see "Core Resource Utilization,"
page 42.
3. Based on 36K block RAMs.
4. Performance numbers listed are for Virtex-6 FPGAs. For more
complete performance data, see "Performance," page 44.
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DS730 September 21, 2010
www.xilinx.com
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Product Specification